參數(shù)資料
型號(hào): FAN7527BN
廠商: Fairchild Semiconductor
文件頁數(shù): 5/12頁
文件大小: 1509K
描述: IC PFC CTRLR TRANSITION 8DIP
標(biāo)準(zhǔn)包裝: 50
模式: 間歇(躍遷)
電流 - 啟動(dòng): 60µA
電源電壓: 11.5 V ~ 30 V
工作溫度: -25°C ~ 125°C
安裝類型: 通孔
封裝/外殼: 8-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 8-DIP
包裝: 管件
產(chǎn)品目錄頁面: 1222 (CN2011-ZH PDF)
其它名稱: FAN7527BN_NL
FAN7527BN_NL-ND
 
?2003 Fairchild Semiconductor Corporation
 
www.fairchildsemi.com
FAN7527B " Rev. 1.0.3
5
 
Electrical Characteristics
V
CC
= 14 V, -25癈 d T
A
 d 125癈, unless otherwise stated.
Symbol
Parameter
Conditions
Min.     Typ.
Max.     Unit
Under-Voltage Lockout
V
th(st)
 
tart Threshold Voltage
V
CC
 Increasing
10.5
11.5
12.5
V
H
Y(st)
 
UVLO Hysteresis
2
3
4
V
Supply Current Section
I
ST
 
tartup Supply Current
V
CC
= V
th(st)
-0.2 V
10
60
100
礎(chǔ)
I
CC
 
perating Supply Current
Output Not Switching
 
3
6
mA
I
CC(OVP)
 
perating Current at OVP
V
INV
= 3 V
 
1.7
4.0
mA
I
DCC
 
Dynamic Operating Supply Current   50 kHz, C
I
= 1 nF
 
4
8
mA
Error Amplifier Section
V
REF
 
oltage Feedback Input Threshold
I
REF
 = 0 mA, T
A
 = 25癈
2.465
2.500
2.535
V
25癈 d T
A
 d 125癈
2.440
2.500
2.560
DV
FEF1
 
Line Regulation
14 V d V
CC
 d 25 V
 
0.1
10.0
mV
DV
FEF3
 
emperature Stability of V
REF
(1)
 
-25癈 d T
A
 d 125癈 
 
20
 
mV
I
b(ea)
 
Input Bias Current
-0.5
 
0.5
礎(chǔ)
I
SOURCE
 
utput Source Current
V
M2
 = 4 V
-2
-4
 
mA
I
SINK
 
utput Sink Current
V
M2
 = 4 V
2
4
 
mA
V
EAO(H)
 
utput Upper Clamp Voltage
(1)
 
I
SOURCE
 = 0.1 mA
 
6
 
V
V
EAO(L)
 
utput Lower Clamp Voltage
(1)
 
I
SINK
 = 0.1 mA
 
2.25
 
V
G
V
 
Large Signal Open-Loop Gain
(1)
 
60
80
 
dB
PSRR
Power Supply Rejection Ratio
(1)
 
14 V d V
CC
 d 25 V
60
80
 
dB
GBW
Unity Gain Bandwidth
(1)
 
 
1
 
MHZ
SR
lew Rate
(1)
 
 
0.6 
 
V/祍
Multiplier Section
I
b(m)
 
Input Bias Current (Pin 3)
-0.5
 
0.5
礎(chǔ)
DV
M1
 
M1 Input Voltage Range (Pin 3)
 
 
3.8
V
DV
M2
 
M2 Input Voltage Range (Pin 2)
V
REF
 
 
V
REF
+2.5
V
K
Multiplier Gain
(1)
 
V
M1
 = 1 V, V
M2
 = 3.5 V
0.36
0.44
0.52
1 / V
V
OMAX(m)
     Maximum Multiplier Output Voltage   V
INV
 =0 V, V
M1
 = 4 V
1.65
1.80
1.95
V
DK/DT
emperature Stability of K
(1)
 
-25 d T
A
 d 125癈
 
-0.2
 
% / 癈
Current Sense Section
V
IO(CS)
 
Input Offset Voltage
(1)
 
V
M1
 = 0 V, V
M2
 = 2.2 V
-10
3
10
mV
I
b(CS)
 
Input Bias Current
0 V d V
CS
 d 1.7 V 
-1.0 
-0.1 
1.0 
礎(chǔ) 
t
D(CS)
 
urrent Sense Delay to Output
(1)
 
 
200
500
ns
Continued on the following page&
 
 
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