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參數(shù)資料
| 型號： | FAN5069EMTCX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 18/22頁 |
| 文件大?。?/td> | 622K |
| 描述： | IC REG DL BCK/LINEAR 16TSSOP |
| 產(chǎn)品變化通告： | Metallization Mask Rev 18/Apr/2007 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 拓?fù)洌?/td> | 降壓（降壓）同步（1），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數(shù)： | 2 |
| 頻率 - 開關(guān)： | 200kHz |
| 電壓/電流 - 輸出 1： | 控制器 |
| 電壓/電流 - 輸出 2： | 控制器 |
| 帶 LED 驅(qū)動器： | 無 |
| 帶監(jiān)控器： | 無 |
| 帶序列發(fā)生器： | 無 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | 帶卷 (TR) |
?2005 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN5069 Rev. 1.1.5
18
Design Tools
Fairchild application note AN-6010 provides a PSPICE
model and spreadsheet calculator for the PWM regula-
tor, simplifying external component selections and verify-
ing loop stability. The topics covered provide an
understanding of the calculations in the spreadsheet.
The spreadsheet calculator, which is part of AN-6010,
can be used to calculate all external component values
for designing around FAN5069. The spreadsheet pro-
vides optimized compensation components and gener-
ates a Bode Plot to ensure loop stability.
Based on the input values entered, AN-6010s PSPICE
model can be used to simulate Bode Plots (for loop sta-
bility) as well as transient analysis to help customize the
design for a wide range of applications.
Use Fairchild Application Note AN-6005 for prediction of
the losses and die temperatures for the power semicon-
ductors used in the circuit.
AN-6010 and AN-6005 can be downloaded from
www.fairchildsemi.com/apnotes/
.
Layout Considerations
The switching power converter layout needs careful
attention and is critical to achieving low losses and clean
and stable operation. Below are specific recommenda-
tions for good board layout:
?SPAN class="pst FAN5069EMTCX_2464147_4"> Keep the high-current traces and load connections as
short as possible.
?SPAN class="pst FAN5069EMTCX_2464147_4"> Use thick copper boards whenever possible to
achieve higher efficiency.
?SPAN class="pst FAN5069EMTCX_2464147_4"> Keep the loop area between the SW node, low-side
MOSFET, inductor, and the output capacitor as small
as possible.
?SPAN class="pst FAN5069EMTCX_2464147_4"> Route high dV/dt signals, such as SW node, away
from the error amplifier input/output pins. Keep com-
ponents connected to these pins close to the pins.
?SPAN class="pst FAN5069EMTCX_2464147_4"> Place ceramic de-coupling capacitors very close to the
VCC pin.
?SPAN class="pst FAN5069EMTCX_2464147_4"> All input signals are referenced with respect to AGND
pin. Dedicate one layer of the PCB for a GND plane.
Use at least four layers for the PCB.
?SPAN class="pst FAN5069EMTCX_2464147_4"> Minimize GND loops in the layout to avoid EMI-related
issues.
?SPAN class="pst FAN5069EMTCX_2464147_4"> Use wide traces for the lower gate drive to eep the
drive impedances low.
?SPAN class="pst FAN5069EMTCX_2464147_4"> Connect PGND directly to the lower MOSFET source
pin.
?SPAN class="pst FAN5069EMTCX_2464147_4"> Use wide land areas with appropriate thermal vias to
effectively remove heat from the MOSFETs.
?SPAN class="pst FAN5069EMTCX_2464147_4"> Use snubber circuits to minimize high-frequency ring-
ing at the SW nodes.
?SPAN class="pst FAN5069EMTCX_2464147_4"> Place the output capacitor for the LDO close to the
source of the LDO MOSFET.
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