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參數(shù)資料
| 型號： | FAN4822IP |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.5 A POWER FACTOR CONTROLLER, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 213K |
| 代理商： | FAN4822IP |
PRODUCT SPECIFICATION
FAN4822
REV. 1.0.0 7/26/01
7
Q1 Turn-On
The turn-on event consists of the time it takes for the current
through L2 to ramp to the L1 current plus the resonant event
of L2 and the ZVS capacitor. The total event should occur in
a minimum of 350–450ns, but can be longer at the risk of
increasing the total harmonic distortion. Setting these times
equal should minimize conducted and radiated emissions.
Where IL2 is equal to IL1.
The value of L2 is calculated to remain in discontinuous-
mode:
The resonant event occurs in 1/4 of a full sinusoidal cycle.
For example, when a 1/4 cycle occurs in 200ns, the fre-
quency is 1.25MHz.
Rearranging and solving for L2:
The resonant capacitor (CZVS) value is found by setting
equations 2 and 4 equal to each other and solving for CZVS.
Application
Figure 3 displays a typical application circuit for a 500W
ZVS PFC supply. Full design details are covered in applica-
tion note 33, FAN4822 Power Factor Correction With Zero
Voltage Resonant Switching.
Figure 2. Timing Diagrams
t
Q1 OFF
()
t
IL2
=
t
RES
+
400ns
=
(1)
L2
V
BUS
V
RMS MIN
()
t
IL2
×
2P
OUT
×
-----------------------------------------------------------------
=
(2)
f
RES
1
L2
C
ZVS
×
2
π
-----------------------------------
1
4t
RES
×
---------------------
==
(3)
L2
4t
RES2
×
π
2
C
ZVS
×
--------------------------
=
(4)
C
ZVS
4t
RES2
×
2P
OUT
×
π
2
V
BUS
V
RMS MIN
()
t
IL2
×
-----------------------------------------------------------------------------
=
(5)
t2
t3
t1
A. SYSTEM
CLOCK
(INTERNAL)
B. RTCT
C. ZVS GATE (Q2)
D. VDS (Q2)
E. PFC GATE (Q1)
F. VDS (Q1)
G. IL2
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