?/DIV>
4.5   0.7    5.7
2
2    5.6   0.7
IN
sense
K   IAC  Gain  V
R
Line input Power
(2)
where 5.6 is V
EA
maximum output.
PFC Soft-Start
PFC startup is controlled by V
EA
level. Before FBPFC
voltage reaches 2.4V, the V
EA
level is around 2.8V. At
90V
AC
, the PFC soft-start time is 90ms.
PFC Brownout
The AC UVP comparator monitors the AC input voltage.
The FAN4800A/C, FAN4801/02 disables PFC as lower
AC input such that the VRMS is less than 1.05V. The
brownout    voltage    of    FAN4802L    is    lower    than
FAN4801/1S/2, such that the VRMS is less than 0.9V.
Error Amplifier Compensation
The PWM loading of the PFC can be modeled as a
negative resistor because an increase in the input
voltage to the PWM causes a decrease in the input
current.     This     response     dictates     the     proper
compensation   of   the   two   transconductance   error
amplifiers. Figure 46 shows the types of compensation
networks most commonly used for the voltage and
current error amplifiers, along with their respective
return   points.   The   current-loop   compensation   is
returned to VREF to produce a soft-start characteristic
on the PFC: As the reference voltage increases from
0V, it creates a differentiated voltage on IEA, which
prevents the PFC from immediately demanding a full
duty cycle on its boost converter. Complete design is
referred in application note AN-6078SC.
There is an RC filter between R
SENSE
and ISENSE pin.
There are two reasons to add a filter at the ISENSE pin:
1. Protection:    During    startup    or    inrush    current
conditions, there is a large voltage across R
SENSE
,
which is the sensing resistor of the PFC boost
converter. It requires the ISENSE filter to attenuate
the energy.
2. To reduce L, the boost inductor: The ISENSE filter
also can reduce the boost inductor value since the
ISENSE filter behaves like an integrator before the
ISENSE pin, which is the input of the current error
amplifier, IEA.
The ISENSE filter is an RC filter. The resistor value of
the ISENSE filter is between 100& and 50& because
I
OFFSET
x R
FILTER
can generate a negative offset voltage
of IEA. Selecting an R
FILTER
equal to 50& keeps the
offset of the IEA less than 3mV. Design the pole of
ISENSE filter at f
PFC
/6, one sixth of the PFC switching
frequency, so the boost inductor can be reduced six
times without disturbing the stability. The capacitor of
the ISENSE filter, C
FILTER
, is approximately 100nF.
Figure 46. Compensation Network Connection for the
Voltage and Current Error Amplifiers