參數(shù)資料
型號: FAN4802SNY
廠商: Fairchild Semiconductor
文件頁數(shù): 19/24頁
文件大?。?/td> 931K
描述: IC CTLR PFC/PWM COMBO 16-PDIP
標(biāo)準(zhǔn)包裝: 30
模式: 平均電流
頻率 - 開關(guān): 240kHz ~ 268kHz
電流 - 啟動(dòng): 30µA
電源電壓: 11 V ~ 26 V
工作溫度: -40°C ~ 105°C
安裝類型: 通孔
封裝/外殼: 16-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 16-DIP
包裝: 管件
 
?2008 Fairchild Semiconductor Corporation
 
www.fairchildsemi.com
FAN4800A/C, FAN4801/02/02L " Rev. 1.0.3
19
TriFault Detect"
To improve power supply reliability, reduce system
component count, and simplify compliance to UL 1950
safety standards, the FAN4800A/C, FAN4801/02/02L
includes TriFault Detect. This feature monitors FBPFC
for certain PFC fault conditions.
In a feedback path failure, the output of the PFC could
exceed safe operating limits. With such a failure,
FBPFC exceeds its normal operating area. Should
FBPFC go too LOW, too HIGH, or OPEN, TriFault
Detect senses the error and terminates the PFC output
drive.
TriFault detect is an entirely internal circuit. It requires
no external components to serve its protective function.
PFC Over-Voltage Protection
In the FAN4800A/C, FAN4801/02/02L, the PFC OVP
comparator serves to protect the power circuit from
being   subjected   to   excessive voltages if the load
changes suddenly. A resistor divider from the high-
voltage DC output of the PFC is fed to FBPFC. When
the voltage on FBPFC exceeds 2.75V, the PFC output
driver is shut down. The PWM section continues to
operate. The OVP comparator has 250mV of hysteresis
and the PFC does not restart until the voltage at FBPFC
drops below 2.50V. V
DD
  OVP can also serve as a
redundant PFC OVP protection. V
DD
 OVP threshold is
28V with 1V hysteresis.
Selecting PFC R
SENSE
 
R
SENSE
   is   the   sensing   resistor   of   the   PFC   boost
converter. During the steady state, line input current x
R
SENSE
 equals I
GAINMOD
 x 5.7K&.
At full load, the average V
EA
 needs to around 4.5V and
ripple on the VEA needs to be less than 400mV.
Choose the resistance of the sensing resistor:
(
(
)
-
?/DIV>
W?/DIV>
?/DIV>
?/DIV>
?/DIV>
=
?/DIV>
-
?/DIV>
4.5   0.7    5.7
2
2    5.6   0.7
 
 
IN
sense
K   IAC  Gain  V
R
Line input Power
 
(2)
where 5.6 is V
EA
 maximum output.
PFC Soft-Start
PFC startup is controlled by V
EA
  level. Before FBPFC
voltage reaches 2.4V, the V
EA
 level is around 2.8V. At
90V
AC
, the PFC soft-start time is 90ms.
PFC Brownout
The AC UVP comparator monitors the AC input voltage.
The FAN4800A/C, FAN4801/02 disables PFC as lower
AC input such that the VRMS is less than 1.05V. The
brownout    voltage    of    FAN4802L    is    lower    than
FAN4801/1S/2, such that the VRMS is less than 0.9V.
 
Error Amplifier Compensation
The PWM loading of the PFC can be modeled as a
negative resistor because an increase in the input
voltage to the PWM causes a decrease in the input
current.     This     response     dictates     the     proper
compensation   of   the   two   transconductance   error
amplifiers. Figure 46 shows the types of compensation
networks most commonly used for the voltage and
current error amplifiers, along with their respective
return   points.   The   current-loop   compensation   is
returned to VREF to produce a soft-start characteristic
on the PFC: As the reference voltage increases from
0V, it creates a differentiated voltage on IEA, which
prevents the PFC from immediately demanding a full
duty cycle on its boost converter. Complete design is
referred in application note AN-6078SC.
There is an RC filter between R
SENSE
 and ISENSE pin.
There are two reasons to add a filter at the ISENSE pin:
1. Protection:    During    startup    or    inrush    current
conditions, there is a large voltage across R
SENSE
,
which is the sensing resistor of the PFC boost
converter. It requires the ISENSE filter to attenuate
the energy.
2. To reduce L, the boost inductor: The ISENSE filter
also can reduce the boost inductor value since the
ISENSE filter behaves like an integrator before the
ISENSE pin, which is the input of the current error
amplifier, IEA.
The ISENSE filter is an RC filter. The resistor value of
the ISENSE filter is between 100& and 50& because
I
OFFSET
 x R
FILTER
 can generate a negative offset voltage
of IEA. Selecting an R
FILTER
  equal to 50& keeps the
offset of the IEA less than 3mV. Design the pole of
ISENSE filter at f
PFC
/6, one sixth of the PFC switching
frequency, so the boost inductor can be reduced six
times without disturbing the stability. The capacitor of
the ISENSE filter, C
FILTER
, is approximately 100nF.
 
Figure 46. Compensation Network Connection for the
Voltage and Current Error Amplifiers
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