參數資料
型號: FAN3850AUC19X
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PBGA6
封裝: 1.26 X 0.86 MM, WLCSP-6
文件頁數: 7/11頁
文件大?。?/td> 973K
代理商: FAN3850AUC19X
2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN3850A Rev. 3.0.1
5
FAN3850A
Microphone
Pre-Am
plifier
with
Digita
lOutput
Electrical Characteristics (Continued)
Unless otherwise specified, all limits are guaranteed for TA=25°C, VDD=1.8V, VIN=94dB(SPL), and fCLK=2.4MHz.
Duty Cycle=50% and CMIC=15pF.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
tA
Time from CLOCK transition to
data becoming valid
On falling edge of CLOCK,
SELECT=GND, CLOAD=15pF
18
43
ns
tB
Time from CLOCK transition to
data becoming Hi-Z
On rising edge of CLOCK,
SELECT=GND, CLOAD=15pF
0
5
16
ns
tA
Time from CLOCK transition to
data becoming valid
On rising edge of CLOCK,
SELECT=VDD, CLOAD=15pF
18
56
ns
tB
Time from CLOCK transition to
data becoming Hi-Z
On falling edge of CLOCK,
SELECT=VDD, CLOAD=15pF
0
5
16
ns
fCLK
Input CLOCK Frequency
(8)
Active Mode
1.0
2.4
4.0
MHz
CLKdc
CLOCK Duty Cycle
(4)
40
50
60
%
tWAKEUP
Wake-Up Time
(9)
fCLK=2.4MHz
0.35
2.0
ms
tFALLASLEEP Fall-Asleep Time
(10)
fCLK=2.4MHz
0
0.01
1.0
ms
CLOAD
Load Capacitance on Data
100
pF
Notes:
3.
Pseudo-random noise with triangular probability density function. Bandwidth up to 10MHz.
4.
Guaranteed by characterization.
5.
Assuming that 120dB(SPL) is mapped to 0dBFS.
6.
Assuming an input of -45dBV
7.
Guaranteed by design.
8.
All parameters are tested at 2.4MHz. Frequency range guaranteed by characterization.
9.
Device wakes up when fCLK ≥ 300kHz.
10. Device falls asleep when fCLK ≤ 70kHz.
Figure 3. Interface Timing
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