參數(shù)資料
型號: FAM-50X1S-T40
元件分類: 光收發(fā)
英文描述: FIBER OPTIC TRANSCEIVER, TRANSPONDER, 1530-1565nm, 10331.1Mbps(Tx), 10331.1Mbps(Rx), PANEL MOUNT, SC CONNECTOR
文件頁數(shù): 10/14頁
文件大?。?/td> 242K
代理商: FAM-50X1S-T40
OC-192/STM-64 1550nm Transponder
40km, 65km and 80km transmission
Preliminary Data Sheet
July 10, 2005
Fiberxon Proprietary and Confidential, Do Not Copy or Distribute
Page 5 of 14
Electrical Interface Characteristics
Table 4 - LVDS Input/Output Specification
Parameter
Symbol
Min.
Typical
Max.
Unit
Notes
LVDS interface
Input Differential Voltage
VID
200
mV
Input Differential impedance
RID
80
100
120
Output Differential Voltage
VOD
500
1000
mV
Output Common Mode Voltage
VCMO
Output Differential impedance
ROD
80
100
120
Rise Time/Fall time
Trise/fall
250
ps
Clock Signal Duty Cycle
45
50
55
%
Differantial
Voltage
(V
OD or VID)
VP
VN
Common Mode
Voltage
(V
CMI or VCMD)
Definition of Differantial Voltage Levels
Table 5 - Input Reference Clocks
Parameter
Symbol
Min.
Typical
Max.
Unit
Notes
Input Differential Voltage
VID
400
1800
mV
Differential Input Impedance
RID
80
100
120
Clock signal Duty Cycle
Tw/To
45
55
%
Table 6 - LVTTL Input/Output Pin Characteristics
Parameter
Symbol
Min.
Typical
Max.
Unit
Notes
Input High Voltage
VIH
2.0
Vdd
V
Input Low Voltage
VIL
GND
0.8
V
Output High Voltage
VOH
2.4
Vdd
V
Output Low Voltage
VOL
GND
0.4
V
Transponder Clock Interfaces and Control
There are seven clock interfaces to the transponder. This section details the specific functions, capabilities,
and limitations of each. Note that all clock rates shown are at STM-64/OC-192 rate, but should be scaled
appropriately for other data rates.
The LVPECL TxREFCLK, provided via the 300-pin interface, may be at 1/16 or 1/64 of the transmitted serial
data rate. The TxREFCLK must be synchronous with the TxPICLK. There are several approaches to ensure
this synchronous relationship. The two most common are
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