參數(shù)資料
型號(hào): FAB2200UCX
廠商: Fairchild Semiconductor
文件頁(yè)數(shù): 2/18頁(yè)
文件大小: 0K
描述: IC SUBSYSTEM HDPH AMP G 25-WLCSP
標(biāo)準(zhǔn)包裝: 1
類(lèi)型: D 類(lèi);G 類(lèi)
輸出類(lèi)型: 1-通道(單聲道),帶立體聲耳機(jī)
在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量: 1.2W x 1 @ 8 歐姆; 41mW x 2 @ 32 歐姆
電源電壓: 2.8 V ~ 5.25 V
特點(diǎn): 消除爆音,差分輸入,I²C,靜音,短路和熱保護(hù),關(guān)機(jī),音量控制
安裝類(lèi)型: 表面貼裝
供應(yīng)商設(shè)備封裝: 25-WLCSP
封裝/外殼: 25-UFBGA,WLCSP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱(chēng): FAB2200UCXFSDKR
10
COMMERCIALTEMPERATURERANGE
IDT72V70180 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 128 x 128
TABLE 8 — FRAME INPUT OFFSET REGISTER (FOR) BITS
NOTE:
1. n denotes an input stream number from 0 to 3.
Name(1)
Description
OFn2, OFn1, OFn0
These three bits define how long the serial interface receiver takes to recognize and store bit 0 from the RX input pin: i.e., to
(Offset Bits 2, 1 & 0)
start a new frame. The input frame offset can be selected to +4.5 clock periods from the point where the external frame pulse
input signal is applied to the
F0i input of the device. See Figure 5.
DLEn
(Data Latch Edge)
ST-BUS mode:
DLEn = 0, if clock rising edge is at the point of the bit cell.
DLEn = 1, if when clock falling edge is at the of the bit cell.
GCI mode:
DLEn = 0, if clock falling edge is at the point of the bit cell.
DLEn = 1, if when clock rising edge is at the of the bit cell.
Read/Write Address:
03H.
Reset Value:
0000H.
15
14
13
12
11
10
9876543210
OF32
OF31
OF30
DLE3
OF22
OF21
OF20
DLE2
OF12
OF11
OF10
DLE1
OF02
OF01
OF00
DLE0
FOR Register
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