
10
F29C51004T/F29C51004B 
 V1.0
   November  1998
SyncMOS
F29C51004T/F29C51004B
Table 2. Command Codes
NOTES:
1. 
2. 
3. 
4. 
5. 
RA: Read Address
RD: Read Data
PA: The address of the memory location to be programmed.
PD: The data at the byte address to be programmed.
SA(5): Sector Address
Command 
Sequence
First Bus
Program Cycle
Second Bus
Program Cycle
Third Bus
Program Cycle
Fourth Bus
Program Cycle
Fifth Bus
Program Cycle
Six Bus
Program Cycle
Address 
Data 
Address 
Data 
Address 
Data 
Address 
Data 
Address 
Data 
Address 
Data
Read 
XXXXH 
F0H
Read 
5555H 
AAH 
2AAAH 
55H 
5555H 
F0H 
RA(1) 
RD(2)
Autoselect 
Mode
5555H 
AAH 
2AAAH 
55H 
5555H 
90H
See table 3 for detail.
Byte
Program
5555H 
AAH 
2AAAH 
55H 
5555H 
A0H 
PA 
PD(4)
Chip Erase 
5555H 
AAH 
2AAAH 
55H 
5555H 
80H 
5555H 
AAH 
2AAAH 
55H 
5555H 
10H
Sector Erase
5555H 
AAH 
2AAAH 
55H 
5555H 
80H 
5555H 
AAH 
2AAAH 
55H 
SA(5) 
30H
Chip Erase Cycle 
The F29C51004T/F29C51004B features a chip-
erase operation. The chip erase operation is
initiated by using a specific six-bus-cycle
sequence: two unlock program cycles, a setup
command, two additional unlock program cycles,
and the chip erase command (see Table 2).
The automatic erase begins on the rising edge of
the last WE or CE pulse in the command sequence
and terminates when the data on DQ7 is “1”.
Program Cycle Status Detection 
There are two methods for determining the state
of the F29C51004T/F29C51004B during a
program (erase/write) cycle: DATA Polling (I/O
7
)
and Toggle Bit (I/O
6
).
DATA Polling (I/O
7
) 
The F29C51004T/F29C51004B features DATA
polling to indicate the end of a program cycle.
When the device is in the program cycle, any
attempt to read the device will received the
complement of the loaded data on I/O
7
. Once the
program cycle is completed, I/O
7
 will show true
data, and the device is then ready for the next
cycle.
Toggle Bit (I/O
6
) 
The F29C51004T/F29C51004B also features
another method for determining the end of a
program cycle. When the device is in the program
cycle, any attempt to read the device will result in
l/O
6
 toggling between 1 and 0. Once the program is
completed, the toggling will stop. The device is then
ready for the next operation. Examining the toggle
bit may begin at any time during a program cycle.
Boot Block Protection Enabling/Disabling
The F29C51004T/F29C51004B features
hardware Boot Block Protection. The boot block
sector protection is enabled when high voltage
(12.5V) is applied to OE and A9 pins with CE pin
LOW and WE pin LOW. The sector protection is
disabled when high voltage is applied to OE, CE
and A9 pins with WE pin LOW. Other pins can be
HIGH or LOW. This is shown in table 1.
Autoselect  Mode
The F29C51004T/F29C51004B features an
Autoselect mode to identify boot block locking
status, device ID and manufacturer ID.
Entering Autoselect mode is accomplished by
applying a high voltage (VH) to the A9 Pin, or
through a sequence of commands (as shown in
table 2). Device will exit this mode once high
voltage on A9 is removed or another command is
loaded into the device.