參數(shù)資料
型號(hào)： EZ4102
廠商： LSI Corporation
英文描述： A Compact, High-Performance,32-bit MIPS Microprocessor(緊密的、高性能、32位 MIPS級(jí)微處理器)
中文描述： 緊湊型，高性能,32位MIPS微處理器（緊密的，高性能，32位的MIPS級(jí)微處理器）
文件頁(yè)數(shù)： 1/28頁(yè)
文件大小： 231K
代理商： EZ4102
September 1999
Copyright 1998, 1999 by LSI Logic Corporation. All rights reserved.
1
The TinyRISC EZ4102 EasyMACRO subsystem is a compact, high-
performance, 32-bit MIPS microprocessor subsystem implemented in LSI
Logic’s G11 technology. The EZ4102 combines the TinyRISC CPU
with the most commonly used blocks (such as a bus controller, MMU,
and EJTAG) to simplify system-on-a-chip design and reduce time to
market. A bus controller module (FBusMACRO) and RAMs are also
available from LSI Logic to help speed your CoreWare
design.
The EZ4102 is appropriate for any embedded application that demands
low power with code compression, and can be easily designed into a
wide range of products. Figure 1 shows the EZ4102 and how it interfaces
with system logic in a typical design.
Figure 1
EZ4102 in a Typical System
The EZ4102 is powered by either 2.5 V or 1.8 V. For 2.5 V operation, the
EZ4102 is rated at 85 MHz (worst case conditions) with a performance
of 85 MIPS peak and 68 MIPS sustainable. For 1.8 V operation, the
EZ4102 is rated at 50 MHz (worst case conditions) with a performance
of 50 MIPS peak and 40 MIPS sustainable. The EZ4102 utilizes G11
32-bit TinyRISC
4102 CPU
and
FastMDU
EZ4102 EasyMACRO Subsystem
Two 32-bit Timers
UART
EJTAG
FlexLink
CBus
Caches and Tags
BBus
EJTAG Interface
SerialICE-1 Interface
MMU
EJTAG Extended Debug MACRO (PC Trace)
BIU and Cache
Controller (BBCC)
TLB RAM
PC Trace Output
FBus
Clock
Controller
FBusMACRO
TinyRISC EZ4102
EasyMACRO Microprocessor
Preliminary Datasheet
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