參數(shù)資料
型號: EZ4021
英文描述: EZ4021 MiniRISC microprocessor core
中文描述: EZ4021 MiniRISC微處理器核心
文件頁數(shù): 1/2頁
文件大?。?/td> 49K
代理商: EZ4021
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The EZ4021 extends the LSI Logic MIPS MiniRISC family with a high
performance 64-bit microprocessor. The EZ4021 EasyMACROTM is an optimized
implementation of a synthesizeable core that operates up to 250MHz under worst
case conditions. With its 275 Dhrystone MIPS 2.1 performance, compact area,
and low power consumption rating, the EZ4021 is well prepared to meet the
embedded system designer’s growing demand for high performance 64-bit
applications.
The EZ4021 EasyMACRO physical implementation facilitates the re-use of the
core in customers’ designs. System designers do not require detailed knowledge
of the core for use in a system-on-a-chip design. Optimized for frequency and
size, the core is a highly integrated solution that is comprised of the MiniRISC
EZ4021 64-bit CPU and CPU sub-system. Specifically designed using industry-
standard, third party EDA tools (including simulation, synthesis, static timing
analysis and ATPG), the EZ4021 further enhances LSI Logic’s MIPS-based
embedded processor line. The EZ4021 EasyMACRO is designed for rapid system
on a chip ASIC integration through LSI Logic’s CoreWare design methodology.
With an operating frequency of 250MHz, the 64-bit EZ4021 microprocessor is
ideally suited for performance driven applications such as set-top boxes,
advanced networking systems, high-end printers and office systems.
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QuickBus
EZ4021
Instruction Cache (16KB 2-way)
I-Cache Controller
Integer
Data Path
Module
CPU
Data Path
Control
Module
Bus
Interface
Unit
CPO
MMU
EJTAG
Interface
D-Cache Controller
Data Cache (16KB 2-way)
EZ4021 Block Diagram
MIPS-III ISA Standard
250 MHz (under worst case conditions)
275 Dhrystone MIPS 2.1 Performance
Harvard Cache Architecture
Integrated 2 way set associative 16K
Instruction Cache and 16K write-back or
write-through Data Cache
Bus Snooping enabling cache coherency
in a multi-processing environment
Compact EasyMACRO size: 12 square mm
- includes 16K Instruction and 16K Data
Caches
Low power consumption: 2.6mW/MHz
Integrated non-intrusive EJTAG Debug
with enhanced break functions &
PC Trace
Low-operating voltage: 1.8V
Future Options:
- Integrated FPU
- Code Compression
- Configurable Cache
- AMBA Interface
EasyMacro: optimized for frequency and
area
Designed for Rapid SoC integration
Support by Industry Standard Toolchains
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