1-10 Revision 10 Boundary Scan Testing (BST) All eX devices are IEEE 1149.1 compliant. eX devices offer s" />
參數(shù)資料
型號(hào)： EX64-TQG100I
廠商： Microsemi SoC
文件頁(yè)數(shù)： 6/48頁(yè)
文件大?。?/td> 0K
描述： IC FPGA ANTIFUSE 3K 100-TQFP
標(biāo)準(zhǔn)包裝： 90
系列： EX
邏輯元件/單元數(shù)： 128
輸入/輸出數(shù)： 56
門數(shù)： 3000
電源電壓： 2.3 V ~ 2.7 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
eX FPGA Architecture and Characteristics
1-10
Revision 10
Boundary Scan Testing (BST)
All eX devices are IEEE 1149.1 compliant. eX devices offer superior diagnostic and testing capabilities by
providing Boundary Scan Testing (BST) and probing capabilities. These functions are controlled through
the special test pins (TMS, TDI, TCK, TDO and TRST). The functionality of each pin is defined by two
available modes: Dedicated and Flexible, and is described in Table 1-4. In the dedicated test mode, TCK,
TDI, and TDO are dedicated pins and cannot be used as regular I/Os. In flexible mode (default mode),
TMS should be set HIGH through a pull-up resistor of 10 k
. TMS can be pulled LOW to initiate the test
sequence.
Dedicated Test Mode
In Dedicated mode, all JTAG pins are reserved for BST; designers cannot use them as regular I/Os. An
internal pull-up resistor is automatically enabled on both TMS and TDI pins, and the TMS pin will function
as defined in the IEEE 1149.1 (JTAG) specification.
To select Dedicated mode, users need to reserve the JTAG pins in Microsemi's Designer software by
checking the Reserve JTAG box in the Device Selection Wizard (Figure 1-12). JTAG pins comply with
LVTTL/TTL I/O specification regardless of whether they are used as a user I/O or a JTAG I/O. Refer to
page 1-18 for detailed specifications.
Flexible Mode
In Flexible Mode, TDI, TCK and TDO may be used as either user I/Os or as JTAG input pins. The internal
resistors on the TMS and TDI pins are disabled in flexible JTAG mode, and an external 10 k
pull-
resistor to VCCI is required on the TMS pin.
To select the Flexible mode, users need to clear the check box for Reserve JTAG in the Device Selection
Wizard in Microsemi's Designer software. The functionality of TDI, TCK, and TDO pins is controlled by
the BST TAP controller. The TAP controller receives two control inputs, TMS and TCK. Upon power-up,
the TAP controller enters the Test-Logic-Reset state. In this state, TDI, TCK, and TDO function as user
I/Os. The TDI, TCK, and TDO pins are transformed from user I/Os into BST pins when the TMS pin is
LOW at the first rising edge of TCK. The TDI, TCK, and TDO pins return to user I/Os when TMS is held
HIGH for at least five TCK cycles.
Table 1-4 Boundary Scan Pin Functionality
Dedicated Test Mode
Flexible Mode
TCK, TDI, TDO are dedicated BST pins
TCK, TDI, TDO are flexible and may be used as I/Os
No need for pull-up resistor for TMS and TDI
Use a pull-up resistor of 10 k
on TMS
Figure 1-12 Device Selection Wizard
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