參數資料
型號: EVAL-SSM2517Z
廠商: Analog Devices Inc
文件頁數: 7/16頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR SSM2517
標準包裝: 1
系列: *
Data Sheet
SSM2517
Rev. B | Page 15 of 16
APPLICATIONS INFORMATION
LAYOUT
As output power increases, care must be taken to lay out PCB
traces and wires properly among the amplifier, load, and power
supply. A good practice is to use short, wide PCB tracks to
decrease voltage drops and minimize inductance. The PCB
layout engineer must avoid ground loops where possible to
minimize common-mode current associated with separate paths
to ground. Ensure that track widths are at least 200 mil per inch
of track length for lowest DCR, and use 1 oz or 2 oz copper PCB
traces to further reduce IR drops and inductance. A poor layout
increases voltage drops, consequently affecting efficiency. Use
large traces for the power supply inputs and amplifier outputs to
minimize losses due to parasitic trace resistance.
Proper grounding guidelines help to improve audio performance,
minimize crosstalk between channels, and prevent switching
noise from coupling into the audio signal. To maintain high
output swing and high peak output power, the PCB traces that
connect the output pins to the load, as well as the PCB traces to
the supply pins, should be as wide as possible to maintain the
minimum trace resistances. It is also recommended that a large
ground plane be used for minimum impedances.
In addition, good PCB layout isolates critical analog paths from
sources of high interference. High frequency circuits (analog
and digital) should be separated from low frequency circuits.
Properly designed multilayer PCBs can reduce EMI emissions
and increase immunity to the RF field by a factor of 10 or more,
compared with double-sided boards. A multilayer board allows
a complete layer to be used for the ground plane, whereas the
ground plane side of a double-sided board is often disrupted by
signal crossover.
POWER SUPPLY DECOUPLING
To ensure high efficiency, low total harmonic distortion (THD),
and high PSRR, proper power supply decoupling is necessary.
Noise transients on the power supply lines are short-duration
voltage spikes. These spikes can contain frequency components
that extend into the hundreds of megahertz.
The power supply inputs must be decoupled with a good quality,
low ESL, low ESR capacitor, with a minimum value of 4.7 μF
for the PVDD pin and 0.1 μF for the VDD pin. This capacitor
bypasses low frequency noises to the ground plane. For high
frequency transient noises, use a 0.1 μF capacitor as close as
possible to the PVDD and VDD pins of the device. Placing the
decoupling capacitors as close as possible to the SSM2517 helps
to maintain efficient performance.
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