參數(shù)資料
型號： EVAL-ADV7189EBM
廠商： Analog Devices, Inc.
英文描述： Multiformat SDTV Video Decoder
中文描述： 標(biāo)清多格式視頻解碼器
文件頁數(shù)： 65/104頁
文件大?。?/td> 890K
代理商： EVAL-ADV7189EBM
ADV7189
REGISTER ACCESSES
The MPU can write to or read from all of the ADV7189’s
registers, except the Subaddress register, which is write-only.
The Subaddress register determines which register the next read
or write operation accesses. All communications with the part
through the bus start with an access to the Subaddress register.
Then, a read/write operation is performed from/to the target
address, which then increments to the next address until a Stop
command on the bus is performed.
Rev. A | Page 65 of 104
REGISTER PROGRAMMING
The following tables describe each register in terms of its
configuration. The Communications register is an 8-bit, write-
only register. After the part has been accessed over the bus and a
read/write operation is selected, the subaddress is set up. The
Subaddress register determines to/from which register the
operation takes place. Table 172 lists the various operations
under the control of the Subaddress register for the control port.
Table 173 lists the various readback registers under the control
of the Subaddress register for the VBI port.
Register Select (SR7-SR0)
These bits are set up to point to the required starting address.
I
2
C SEQUENCER
An I
2
C sequencer is employed in cases where a parameter
exceeds eight bits, and is therefore distributed over two or more
I
2
C registers (e.g., HSB [11:0]).
When such a parameter is changed using two or more I
2
C write
operations, the parameter may hold an invalid value for the
time between the first I
2
C finishing and the last I
2
C being
completed. In other words, the top bits of the parameter may
already hold the new value while the remaining bits of the
parameter still hold the previous value.
To avoid this problem, the I
2
C sequencer holds the already
updated bits of the parameter in local memory; all bits of the
parameter are updated together once the last register write
operation has completed.
The correct operation of the I
2
C sequencer relies on the
following:
All I
2
C registers for the parameter in question must be
written to in order of ascending addresses. (e.g., for
HSB[10:0], write to Address 34h first, followed by 35h).
No other I
2
C taking place between the two (or more) I
2
C
writes for the sequence (e.g., for HSB[10:0], write to
Address 0x34 first, immediately followed by 0x35).
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