參數(shù)資料
型號(hào)： EVAL-ADF4351EB1Z
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 18/28頁(yè)
文件大?。?/td> 0K
描述： BOARD 1 EVAL FOR ADF4351
標(biāo)準(zhǔn)包裝： 1
系列： *
Data Sheet
ADF4351
Rev. 0 | Page 25 of 28
APPLICATIONS INFORMATION
DIRECT CONVERSION MODULATOR
Direct conversion architectures are increasingly being used
to implement base station transmitters. Figure 34 shows how
Analog Devices, Inc., parts can be used to implement such a
system.
Figure 34 shows the AD9788 TxDAC used with the ADL5375.
The use of dual integrated DACs, such as the AD9788 with its
specified ±2% FSR and ±0.001% FSR gain and offset character-
istics, ensures minimum error contribution (over temperature)
from this portion of the signal chain.
The local oscillator (LO) is implemented using the ADF4351. The
low-pass filter was designed using ADIsimPLL for a channel
spacing of 200 kHz and a closed-loop bandwidth of 35 kHz.
The LO ports of the ADL5375 can be driven differentially from
the complementary RFOUTA± outputs of the ADF4351. This setup
provides better performance than a single-ended LO driver and
eliminates the use of a balun to convert from a single-ended LO
input to the more desirable differential LO input for the ADL5375.
The typical rms phase noise (100 Hz to 5 MHz) of the LO in this
configuration is 0.61° rms.
The ADL5375 accepts LO drive levels from 6 dBm to +6 dBm.
The optimum LO power can be software programmed on the
ADF4351, which allows levels from 4 dBm to +5 dBm from
each output.
The RF output is designed to drive a 50 load, but it must be
ac-coupled, as shown in Figure 34. If the I and Q inputs are
driven in quadrature by 2 V p-p signals, the resulting output
power from the ADL5375 modulator is approximately 2 dBm.
09800-
034
AD9788
TxDAC
MODULATED
DIGITAL
DATA
OUT2_N
OUT1_P
OUT1_N
OUT2_P
LOW-PASS
FILTER
LOW-PASS
FILTER
2700pF
1200pF
39nF
680
360
IBBP
IBBN
QBBP
QBBN
LOIP
LOIN
S
P
I-
CO
M
P
AT
IBL
E
S
E
RI
AL
BUS
ADF4351
VVCO
CPGND
AGND
DGND
RFOUTB–
RFOUTB+
CPOUT
1nF
4.7k
RSET
LE
DATA
CLK
REFIN
fREFIN
VTUNE
DVDD AVDD CE
MUXOUT
10
28
16
29
1
2
3
22
8
31
9
11
18
21
27
VDD
LOCK
DETECT
51
51
51
51
51
AGNDVCO
14
15
19
23
24
25
30
LD
17
20
7
PDBRF
26
SDGND
TEMP VCOM
VREF
6
32
SDVDD
VP
5
SW
10pF
0.1F 10pF
0.1F
4
ADL5375
RFOUT
QUADRATURE
PHASE
SPLITTER
DSOP
RFOUTA–
RFOUTA+
13
12
1nF
3.9nH
VVCO
LPF
Figure 34. Direct Conversion Modulator
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