參數(shù)資料
型號(hào)： EVAL-ADF4154EB1
廠商： Analog Devices, Inc.
元件分類： 通信、網(wǎng)絡(luò)模塊及開(kāi)發(fā)工具
英文描述： Fractional-N Frequency Synthesizer
中文描述： 分?jǐn)?shù)N頻率合成器
文件頁(yè)數(shù)： 6/20頁(yè)
文件大?。?/td> 470K
代理商： EVAL-ADF4154EB1
ADF4154
PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS
Rev. 0 | Page 6 of 20
ADF4154
TOP VIEW
(Not to Scale)
AGND
4
RF
IN
B
RF
IN
A
AV
DD
REF
IN
5
6
7
8
LE
DATA
CLK
SDV
DD
DGND
13
12
11
10
R
SET
CP
1
2
CPGND
3
V
P
DV
DD
MUXOUT
16
15
14
9
0
Figure 3. TSSOP Pin Configuration
0
15
MUXOUT
LE
DATA
CLK
SDV
DD
11
14
13
12
1
2
3
4
5
2
6
7
8
9
1
D
D
R
I
A
D
A
D
RF
IN
A
RF
IN
B
AGND
AGND
CPGND
1
1
1
1
ADF4154
TOP VIEW
C
R
S
V
P
D
D
D
D
PIN 1
Figure 4. LFCSP Pin Configuration
Table 4. Pin Function Descriptions
TSSOP
LFCSP
1
19
Mnemonic
R
SET
Description
Connecting a resistor between this pin and ground sets the maximum charge pump output current.
The relationship between I
CP
and R
SET
is
5
25
I
SET
CP
R
.
max
=
where
R
SET
= 5.1 k and
I
CPma
x
= 5 mA.
Charge Pump Output. When enabled, this provides ±I
CP
to the external loop filter, which in turn drives
the external VCO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a
small bypass capacitor, typically 100 pF (see Figure 18).
Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.
Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be
placed as close as possible to this pin. AV
DD
has a value of 3 V ± 10%. AV
DD
must have the same voltage
as DV
DD
.
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and an equivalent input
resistance of 100 k (see Figure 17). This input can be driven from a TTL or CMOS crystal oscillator, or it
can be ac-coupled.
Digital Ground.
Σ
- Power. Decoupling capacitors to the digital ground plane should be placed as close as possible to
this pin. SDV
DD
has a value of 3 V ± 10%. SDV
DD
must have the same voltage as DV
DD
.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This input is a
high impedance CMOS input.
Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of
the four latches, the latch being selected using the control bits.
This multiplexer output allows either the RF lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should
be placed as close as possible to this pin. DV
DD
has a value of 3 V ± 10%. DV
DD
must have the same
voltage as AV
DD
.
Charge Pump Power Supply. This should be greater than or equal to V
DD
. In systems where V
DD
is 3 V, it
can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
2
20
CP
3
4
5
1
2, 3
4
CPGND
AGND
RF
IN
B
6
7
5
6, 7
RF
IN
A
AV
DD
8
8
REF
IN
9
10
9, 10
11
DGND
SDV
DD
11
12
CLK
12
13
DATA
13
14
LE
14
15
MUXOUT
15
16, 17
DV
DD
16
18
V
P
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