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參數(shù)資料
| 型號(hào)： | EVAL-AD976ACB |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 2/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD976A |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 輸入范圍： | ±10 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 100mW @ 200kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD976A |
| 已供物品： | 板，CD |
| 相關(guān)產(chǎn)品： | AD976ACRSZ-ND - IC ADC 16BIT 200KSPS 28SSOP AD976ACRZ-ND - IC ADC 16BIT 200KSPS 28SOIC AD976CRZ-ND - IC ADC 16BIT 100KSPS 28SOIC AD976CRSZ-ND - IC ADC 16BIT 100KSPS 28SSOP AD976CNZ-ND - IC ADC 16BIT 100KSPS 28DIP AD976BRSZ-ND - IC ADC 16BIT 100KSPS 28SSOP AD976BNZ-ND - IC ADC 16BIT 100KSPS 28-DIP AD976ACNZ-ND - IC ADC 16BIT 200KSPS 28DIP AD976AARSZ-ND - IC ADC 16BIT 200KSPS 28SSOP AD976ARZRL-ND - IC ADC 16BIT 100KSPS 28SOIC 更多... |
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AD976/AD976A
–10–
REV. C
OFFSET AND GAIN ADJUSTMENT
The AD976/AD976A is factory trimmed to minimize gain,
offset and linearity errors. In some applications, where the ana-
log input signal is required to meet the full dynamic range of the
ADC, the gain and offset errors need to be externally trimmed
to zero. Figure 7 shows the required trim circuitry to correct for
these offset and gain errors. Figure 8 shows the bipolar transfer
characteristic of the AD976/AD976A.
Where adjustment is required, offset error must be corrected
before gain error. To achieve this, trim the offset resistor R3
while the input voltage is 1/2 LSB below ground. By applying
a voltage of –152.6
V at the input and adjusting the potentiom-
eter until the major carry transition is located between 1111
1111 1111 1111 and 0000 0000 0000 0000, the internal offset
can be corrected. To adjust the gain error, an analog signal
should be input at either the first code transition (ADC negative
full-scale) or the last code transition (ADC positive full-scale).
Thus, to adjust for full-scale error, an input voltage of 9.999542 V
(FS/2–3/2 LSBs) can be applied to the input and R4 should be
adjusted until the output code flickers between the last positive
code transition 0111 1111 1111 1111 and 0111 1111 1111 1110.
Should the first code transition need adjusting, the trim procedure
should consist of applying an analog input signal of –9.999847 V
(–FS/2 + 1/2 LSB) to the input and adjusting the trim until
the output code flickers between 1000 0000 0000 0000 and
1000 0000 0000 0001.
The external 200
and 33.2K resistor shown in the data sheet for
the AD976 provide compensation for an internal adjustment of the
offset and gain which allows calibration with a single supply. These
resistors may not be required in some applications but it should be
noted that their removal will result in offset and gain errors in
addition to those listed in the electrical specifications of the data
sheet. Tables I and II illustrate the worst case range for Bipolar
Zero (offset) error and Full-Scale (gain) error for the AD976 and
the AD976A. All error terms are with respect to the A/D (i.e., a
negative offset in the table would have to be corrected with an
externally applied positive voltage).
R5
576k
+5V
R4
50k
VIN
AGND1
REF
CAP
AGND2
10V
INPUT
R2
33.2k
C2
2.2 F
AD976/
AD976A
R1
200
C1
2.2 F
R3
50k
Figure 7. Input Connection with Offset and Gain Adjustment
OUTPUT
CODE
011...111
011...110
000...001
000...000
111...111
100...010
100...001
100...000
0V
(VREF/2) – 1 LSB
(VREF/2) + 1 LSB
+ FS – 1 LSB
FS = VREFV
1LSB =
FS
65536
VREF/2
VIN = (AIN(+) - AIN(-)) – INPUT VOLTAGE
Figure 8. The Bipolar Transfer Characteristic of the
AD976/AD976A
Table I. Offset and Gain Error for AD976
With Both External
Without the External
With the External 33.2K
Without Either External
Error Term
Resistors Included
33.2K Resistor
Resistor Grounded
Resistors Included
Offset Error
–10 mV < Error < 10 mV
–25 mV < Error < –5 mV
–40 mV < Error < –15 mV
+Full Scale
–0.50% < Error < 0.50%
1
–0.05% < Error < 0.95%
–0.65% < Error < 0.35%
0.55% < Error < 1.90%
Error
–0.25% < Error < 0.25%2
–Full Scale
–0.50% < Error < 0.50%1
0.25% < Error < 1.25%
–0.65% < Error < 0.35%
–2.5% < Error < –1.0%
Error
–0.25% < Error < 0.25%
2
Table II. Offset and Gain Error for AD976A
With Both External
Without the External
With the External 33.2K
Without Either External
Error Term
Resistors Included
33.2K Resistor
Resistor Grounded
Resistors Included
Offset Error
–10 mV < Error < 10 mV
–25 mV < Error < –5 mV
–55 mV < Error < –25 mV
+Full Scale
–0.50% < Error < 0.50%
1
–0.05% < Error < 0.95%
–0.65% < Error < 0.35%
1.0% < Error < 2.50%
Error
–0.25% < Error < 0.25%
2
–Full Scale
–0.50% < Error < 0.50%
1
0.25% < Error < 1.25%
–0.65% < Error < 0.35%
–3.50% < Error < –1.75%
Error
–0.25% < Error < 0.25%
2
NOTES
1For A grade part.
2For B grade part.
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