參數(shù)資料
型號： EVAL-AD7986EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 14/28頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD7986
產(chǎn)品培訓(xùn)模塊： Motor Control
標準包裝： 1
系列： PulSAR®
ADC 的數(shù)量： 1
位數(shù)： 18
采樣率（每秒）： 2M
數(shù)據(jù)接口： 串行
輸入范圍： ±VREF
在以下條件下的電源（標準）： 29mW @ 2MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7986
已供物品： 板
AD7986
Rev. B | Page 21 of 28
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7986 devices are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7986 devices is
shown in Figure 29, and the corresponding timing is given in
With SDI high, a rising edge on CNV initiates a conversion, selects
the CS mode, and forces SDO to high impedance. In this mode,
CNV must be held high during the conversion phase and the
subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator. When the conversion is complete, the AD7986 enters
the acquisition phase and powers down. Each ADC result can
be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are then
clocked by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can be used to capture
the data, a digital host using the SCK falling edge allows a faster
reading rate, provided that it has an acceptable hold time. After
the 18th SCK falling edge, SDO returns to high impedance and
another AD7986 can be read.
AD7986
SDI
SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
CS1
CS2
AD7986
SDI
SDO
CNV
SCK
07956-
022
Figure 29. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
ACQUISITION (n)
ACQUISITION
(n + 1)
ACQUISITION
(n – 1)
1
2
BEGIN DATA (n – 1)
CONVERSION (n)
END DATA (n – 1)
SCK
CNV
SDO
16
17
CONVERSION (n – 1)
END DATA (n – 2)
0
tCYC
tCONV
tDATA
tACQ
tCONV
tDATA
(I/O QUIET
TIME)
(I/O QUIET
TIME)
18
16
17
18
1
17
16
15
2
0
1
2
SDI
(QUIET
TIME)
tHSDICNV
tSSDICNV
tEN
tHSDO
tSCK
tDIS
tHSDO
tQUIET
tDSDO
07956-
120
Figure 30. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing
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