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參數(shù)資料
| 型號(hào)： | EVAL-AD7923CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 4/24頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7923 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 0 ~ 2.5 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 7.5mW @ 200kSPS，5 V |
| 工作溫度： | -40°C ~ 125°C |
| 已用 IC / 零件： | AD7923 |
| 已供物品： | 板，CD |
| 相關(guān)產(chǎn)品： | AD7923BRUZ-REEL7TR-ND - IC ADC 12BIT 4CH W/SEQ 16TSSOP AD7923BRUZ-REEL-ND - IC ADC 12BIT 4CH W/SEQ 16TSSOP AD7923BRUZ-ND - IC ADC 12BIT 4CH W/SEQ 16TSSOP |
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AD7923
Data Sheet
Rev. D | Page 12 of 24
CONTROL REGISTER DESCRIPTIONS
The control register on the AD7923 is a 12-bit, write-only
register. Data is loaded from the DIN pin of the AD7923 on the
falling edge of SCLK. The data is transferred on the DIN line at
the same time that the conversion result is read from the part.
The data transferred on the DIN line corresponds to the
AD7923 configuration for the next conversion. This requires
16 serial clocks for every data transfer. Only the information
provided on the first 12 falling clock edges (after CS falling
edge) is loaded to the control register. MSB denotes the first bit
in the data stream. The bit functions are outlined in Table 5.
Table 5. Control Register Bit Functions
MSB
LSB
WRITE
SEQ1
DONTC
ADD1
ADD0
PM1
PM0
SEQ0
DONTC
RANGE
CODING
Table 6.
Bit
Name
Description
11
WRITE
The value written to this bit of the control register determines whether the following 11 bits are loaded to the
control register. If this bit is a 1, the following 11 bits are written to the control register. If it is a 0, the remaining
11 bits are not loaded to the control register and it remains unchanged.
10
SEQ1
The SEQ1 bit in the control register is used with the SEQ0 bit to control the use of the sequencer function (see
7–6
ADD1
ADD0
These two address bits are loaded at the end of the present conversion and select which analog input channel is
converted in the next serial transfer, or they can also be used to select the final channel in a consecutive sequence,
as described in Table 9. The selected input channel is decoded, as shown in Table 7. The next channel to be
converted on is selected by the mux on the 14th SCLK falling edge. Channel address bits corresponding to the
conversion result are also output on the DOUT serial data stream prior to the 12 bits of data (see the Serial Interface
section).
5, 4
PM1
PM0
Power management bits. These two bits decode the mode of operation of the AD7923, as shown in Table 8.
3
SEQ0
The SEQ0 bit in the control register is used with the SEQ1 bit to control the use of the sequencer function.
(see Table 9).
2, 9–8
DONTC
Don’t care.
1
RANGE
This bit selects the analog input range to be used on the AD7923. If it is set to 0, the analog input range extends from
0 V to 2 × REFIN. If it is set to 1, the analog input range extends from 0 V to REFIN (for the next conversion). For the 0 V
to 2 × REFIN range, AVDD = 4.75 V to 5.25 V.
0
CODING
This bit selects the type of output coding the AD7923 uses for the conversion result. If this bit is set to 0, the output
coding for the part is twos complement. If this bit is set to 1, the output coding from the part is straight binary (for
the next conversion).
Table 7. Channel Selection
ADD1
ADD0
Analog Input Channel
0
VIN0
0
1
VIN1
1
0
VIN2
1
VIN3
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