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參數(shù)資料
| 型號(hào)： | EVAL-AD7888CB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | +2.7 V to +5.25 V, Micropower, 8-Channel, 125 kSPS, 12-Bit ADC in 16-Lead TSSOP |
| 中文描述： | 2.7 V至5.25 V，微功耗，8通道，125 kSPS的，12位ADC的16引腳TSSOP |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 164K |
| 代理商： | EVAL-AD7888CB |
REV. 0
AD7888
–13–
SERIAL INTERFACE
Figure 16 shows the detailed timing diagram for serial interfac-
ing to the AD7888. The serial clock provides the conversion
clock and also controls the transfer of information to and from
the AD7888 during conversion.
CS
initiates the data transfer and conversion process. For the
autoshutdown mode, the first falling edge of SCLK after the
falling edge of
CS
wakes up the part. In all cases, it gates the
serial clock to the AD7888 and puts the on-chip track/hold into
track mode. The input signal is sampled on the second rising
edge of the SCLK input after the falling edge of
CS
. Thus, the
first one and one-half clock cycles after the falling edge of
CS
is
when the acquisition of the input signal takes place. This time is
denoted as the acquisition time (t
ACQ
). In autoshutdown mode,
the acquisition time must allow for the wake-up time of 5
μ
s. The
on-chip track/hold goes from track mode to hold mode on the
second rising edge of SCLK and a conversion is also initiated on
this edge. The conversion process takes a further fourteen and
one-half SCLK cycles to complete. The rising edge of
CS
will
put the bus back into three-state. If
CS
is left low a new conver-
sion will be initiated.
The input channel that is sampled is the one selected in the
previous write to the Control Register. Thus, the user must
DONTC
REF
ZERO
ADD2
ADD1
ADD0
PM1
PM0
SCLK
1
5
6
15
DOUT
DIN
2
3
4
16
t
1
t
ACQ
t
CONVERT
t
2
t
6
t
7
t
3
t
8
DB11
DB0
DB10
DB9
4 LEADING ZEROS
CS
THREE-
STATE
t
4
t
5
THREE-
STATE
Figure 16. Serial Interface Timing Diagram
write ahead of the channel for conversion. In other words, the
user must write the channel address for the next conversion
while the present conversion is in progress.
Writing of information to the Control Register takes place on
the first eight rising edges of SCLK in a data transfer. The Con-
trol Register is always written to when a data transfer takes
place. The user must be careful to always set up the correct
information on the DIN line when reading data from the part.
Sixteen serial clock cycles are required to perform the conver-
sion process and to access data from the AD7888. In applica-
tions where the first serial clock edge, following
CS
going low, is
a falling edge, this edge clocks out the first leading zero. Thus,
the first rising clock edge on the SCLK clock has the first lead-
ing zero provided. In applications where the first serial clock
edge, following
CS
going low, is a rising edge, the first leading
zero may not be set up in time for the processor to read it cor-
rectly. However, subsequent bits are clocked out on the falling
edge of SCLK so they are provided to the processor on the
following rising edge. Thus, the second leading zero is clocked
out on the falling edge subsequent to the first rising edge. The
final bit in the data transfer is valid on the 16th rising edge,
having being clocked out on the previous falling edge.
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