參數(shù)資料
型號(hào)： EVAL-AD7843CB
廠商： Analog Devices, Inc.
英文描述： Touch Screen Digitizer
中文描述： 觸摸屏數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 3/16頁(yè)
文件大?。?/td> 193K
代理商： EVAL-AD7843CB
REV. 0
AD7843
–3–
Parameter
f
DCLK 2
Limit at T
MIN
, T
MAX
10
2
1.5
10
60
60
200
200
60
10
10
200
0
200
200
Unit
Description
kHz min
MHz max
μ
s min
ns min
ns max
ns max
ns min
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns max
t
ACQ
t
1
t
2
t
33
t
4
t
5
t
6
t
7
t
8
t
93
t
10
t
t
11
Acquisition Time
CS
Falling Edge to First DCLK Rising Edge
CS
Falling Edge to BUSY Three-State Disabled
CS
Falling Edge to DOUT Three-State Disabled
DCLK High Pulsewidth
DCLK Low Pulsewidth
DCLK Falling Edge to BUSY Rising Edge
Data Setup Time Prior to DCLK Rising Edge
Data Valid to DCLK Hold Time
Data Access Time after DCLK Falling Edge
CS
Rising Edge to DCLK Ignored
CS
Rising Edge to BUSY High Impedance
CS
Rising Edge to DOUT High Impedance
NOTES
1
Sample tested at 25
°
C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
CC
) and timed from a voltage level of 1.6 V.
2
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 2.0 V.
4
t
12
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
12
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
1
(T
A
= T
MIN
to T
MAX
, unless otherwise noted; V
CC
= 2.7 V to 3.6 V, V
REF
= 2.5 V)
TO
OUTPUT
PIN
C
L
50pF
1.6V
I
OL
200 A
I
OH
200 A
Figure 1. Load Circuit for Digital Output Timing Specifications
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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