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參數(shù)資料
| 型號(hào)： | EVAL-AD7751EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Energy Metering IC With On-Chip Fault Detection |
| 中文描述： | 電能計(jì)量IC，帶有片上故障檢測(cè) |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 249K |
| 代理商： | EVAL-AD7751EB |
REV. A
AD7751
–5–
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
DV
DD
Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the AD7751.
The supply voltage should be maintained at 5 V
±
5% for specified operation. This pin should be
decoupled with a 10
μ
F capacitor in parallel with a ceramic 100 nF capacitor.
High-Pass Filter Select. This logic input is used to enable the HPF in Channel 1 (the current
channel). A Logic 1 on this pin enables the HPF. The associated phase response of this filter has
been internally compensated over a frequency range of 45 Hz to 1 kHz. The HPF filter should be
enabled in energy metering applications.
Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the AD7751.
The supply should be maintained at 5 V
±
5% for specified operation. Every effort should be made
to minimize power supply ripple and noise at this pin by the use of proper decoupling. This pin
should be decoupled to AGND with a 10
μ
F capacitor in parallel with a ceramic 100 nF capacitor.
Analog Inputs for Channel 1 (Current Channel). These inputs are fully differential voltage inputs
with a maximum signal level of
±
660 mV with respect to Pin V1N for specified operation. The
maximum signal level at these pins is
±
1 V with respect to AGND. Both inputs have internal ESD
protection circuitry and an overvoltage of
±
6 V can also be sustained on these inputs without risk of
permanent damage.
Negative Input Pin for Differential Voltage Inputs V1A and V1B. The maximum signal level at this
pin is
±
1 V with respect to AGND. The input has internal ESD protection circuitry and in addition,
an overvoltage of
±
6 V can be sustained without risk of permanent damage. This input should be
directly connected to the burden resistor and held at a fixed potential, i.e., AGND. See Analog
Input section.
Negative and Positive Inputs for Channel 2 (Voltage Channel). These inputs provide a fully differ-
ential input pair. The maximum differential input voltage is
±
660 mV for specified operation. The
maximum signal level at these pins is
±
1 V with respect to AGND. Both inputs have internal ESD
protection circuitry and an overvoltage of
±
6 V can also be sustained on these inputs without risk of
permanent damage.
Reset Pin for the AD7751. A logic low on this pin will hold the ADCs and digital circuitry in a reset
condition. Bringing this pin logic low will clear the AD7751 internal registers.
Provides Access to the On-Chip Voltage Reference. The on-chip reference has a nominal value of
2.5 V
±
8% and a typical temperature coefficient of 30 ppm/
°
C. An external reference source may also
be connected at this pin. In either case, this pin should be decoupled to AGND with a 1
μ
F ceramic
capacitor and 100 nF ceramic capacitor.
Provides the Ground Reference for the Analog Circuitry in the AD7751, i.e., ADCs and Reference.
This pin should be tied to the analog ground plane of the PCB. The analog ground plane is the
ground reference for all analog circuitry, e.g., antialiasing filters, current and voltage transduc-
ers, etc. For good noise suppression the analog ground plane should only be connected to the digital
ground plane at one point. A star ground configuration will help to keep noisy digital return currents
away from the analog circuits.
Select Calibration Frequency. This logic input is used to select the frequency on the calibration
output CF. Table IV shows how the calibration frequencies are selected.
These logic inputs are used to select one of four possible frequencies for the digital-to-frequency
conversion. This offers the designer greater flexibility when designing the energy meter. See Select-
ing a Frequency for an Energy Meter Application section.
These logic inputs are used to select one of four possible gains for the analog inputs V1A and V1B.
The possible gains are 1, 2, 8 and 16. See Analog Input section.
An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can
be connected across CLKIN and CLKOUT to provide a clock source for the AD7751. The clock
frequency for specified operation is 3.579545 MHz. Crystal load capacitors of between 22 pF
and 33 pF (ceramic) should be used with the gate oscillator circuit.
A crystal can be connected across this pin and CLKIN as described above to provide a clock source
for the AD7751. The CLKOUT pin can drive one CMOS load when an external clock is supplied
at CLKIN or by gate oscillator circuit.
This logic output will go active high when a fault condition occurs. A fault is defined as a condition
under which the signals on V1A and V1B differ by more than 12.5%. The logic output will be reset
to zero when a fault condition is no longer detected. See Fault Detection section.
2
AC/
DC
3
AV
DD
4, 5
V1A, V1B
6
V1N
7, 8
V2N, V2P
9
RESET
10
REF
IN/OUT
11
AGND
12
SCF
13, 14
S1, S0
15, 16
G1, G0
17
CLKIN
18
CLKOUT
19
FAULT
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