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| 型號(hào)： | EVAL-AD7730LEBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 16/53頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7730 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 600 |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±80 mV |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 125mW @ 600SPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7730 |
| 已供物品： | 板，CD |
| 相關(guān)產(chǎn)品： | AD7730LBRUZ-ND - IC ADC TRANSDUCER BRIDGE 24TSSOP AD7730LBRZ-ND - IC ADC TRANSDUCER BRIDGE 24SOIC AD7730LBRUZ-REEL7-ND - IC ADC TRANSDUCER BRIDGE 24TSSOP AD7730LBRZ-REEL-ND - IC ADC TRANSDUCER BRIDGE 24SOIC AD7730LBRUZ-REEL-ND - IC ADC TRANSDUCER BRIDGE 24TSSOP AD7730BRUZ-REEL7-ND - IC ADC BRIDGE TRANSDUCER 24TSSOP AD7730BRUZ-REEL-ND - IC ADC BRIDGE TRANSDUCER 24TSSOP AD7730BRUZ-ND - IC ADC TRANSDUCER BRIDGE 24TSSOP AD7730BNZ-ND - IC ADC TRANSDUCER BRIDGE 24-DIP AD7730BRZ-REEL7TR-ND - IC ADC BRDGE TRANSDCR 24SOIC TR 更多... |
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AD7730/AD7730L
–23–
CIRCUIT DESCRIPTION
The AD7730 is a sigma-delta A/D converter with on-chip digital
filtering, intended for the measurement of wide dynamic range,
low-frequency signals such as those in weigh-scale, strain-gage,
pressure transducer or temperature measurement applications.
It contains a sigma-delta (or charge-balancing) ADC, a calibra-
tion microcontroller with on-chip static RAM, a clock oscillator,
a digital filter and a bidirectional serial communications port.
The part consumes 13 mA of power supply current with a standby
mode which consumes only 25
μA. The part operates from a single
+5 V supply. The clock source for the part can be provided via an
external clock or by connecting a crystal oscillator or ceramic
resonator across the MCLK IN and MCLK OUT pins.
The part contains two programmable-gain fully differential analog
input channels. The part handles a total of eight different input
ranges which are programmed via the on-chip registers. There are
four differential unipolar ranges: 0 mV to +10 mV, 0 mV to
+20 mV, 0 mV to +40 mV and 0 mV to +80 mV and four differen-
tial bipolar ranges:
±10 mV, ±20 mV, ±40 mV and ±80 mV.
The AD7730 employs a sigma-delta conversion technique to
realize up to 24 bits of no missing codes performance. The
sigma-delta modulator converts the sampled input signal into a
digital pulse train whose duty cycle contains the digital informa-
tion. A digital low-pass filter processes the output of the sigma-
delta modulator and updates the data register at a rate that can
be programmed over the serial interface. The output data from
the part is accessed over this serial interface. The cutoff frequency
and output rate of this filter can be programmed via on-chip
registers. The output noise performance and peak-to-peak reso-
lution of the part varies with gain and with the output rate as
shown in Tables I to IV.
The analog inputs are buffered on-chip allowing the part to
handle significant source impedances on the analog input. This
means that external R, C filtering (for noise rejection or RFI
reduction) can be placed on the analog inputs if required. Both
analog channels are differential, with a common-mode voltage
range that comes within 1.2 V of AGND and 0.95 V of AVDD.
The reference input is also differential and the common-mode
range here is from AGND to AVDD.
The part contains a 6-bit DAC that is controlled via on-chip
registers. This DAC can be used to remove TARE values of up
to
±80 mV from the analog input signal range. The resolution
on this TARE function is 1.25 mV for a +2.5 V reference and
2.5 mV with a +5 V reference.
The AD7730 can accept input signals from a dc-excited bridge.
It can also handle input signals from an ac-excited bridge by
using the ac excitation clock signals (ACX and
ACX) to switch
the supplies to the bridge. ACX and
ACX are nonoverlapping
clock signals used to synchronize the external ac supplies that
drive the transducer bridge. These ACX clocks are demodulated
on the AD7730 input.
The AD7730 contains a number of hardware and software
events that set or reset status flags and bits in registers. Table
XVIII summarizes which blocks and flags are affected by the
different events.
Table XVIII. Reset Events
Set Registers
Mode
Filter
Analog
Reset Serial
Set
RDY
Set
STDY
Event
to Default
Bits
Reset
Power-Down
Interface
Pin/Bit
Bit
Power-On Reset
Yes
000
Yes
RESET Pin
Yes
000
Yes
No
Yes
STANDBY Pin
No
As Is
Yes
No
Yes
Mode 011 Write
No
011
Yes
No
Yes
SYNC Pin
No
As Is
Yes
No
Yes
Mode 000 Write
No
000
Yes
No
Yes
Conversion or
No
New
Initial
No
Yes
Cal Mode Write
Value
Reset
Clock 32 1s
Yes
000
Yes
No
Yes
Data Register Read
No
As Is
No
Yes
No
REV. B
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