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| 鍨嬭櫉(h脿o)锛� | EVAL-AD7725CBZ |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 8/28闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | BOARD EVALUATION FOR AD7725 |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| ADC 鐨勬暩(sh霉)閲忥細 | 1 |
| 浣嶆暩(sh霉)锛� | 16 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 900k |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶锛屽苟鑱�(li谩n) |
| 杓稿叆鑼冨湇锛� | ±VREF |
| 鍦ㄤ互涓嬫浠朵笅鐨勯浕婧愶紙妯�(bi膩o)婧�(zh菙n)锛夛細 | 615mW @ 900kSPS |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 宸茬敤 IC / 闆朵欢锛� | AD7725 |
| 宸蹭緵鐗╁搧锛� | 鏉匡紝CD |
| 鐩搁棞(gu膩n)鐢�(ch菐n)鍝侊細 | AD7725BSZ-ND - IC ADC 16BIT PROG 44MQFP |
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REV. A
鈥�16鈥�
AD7725
A
B
A
B
500
AC GROUND
CLKIN
A
B
2pF
VIN(+)
VIN(鈥�)
AD7725
Figure 11. Analog Input Equivalent Circuit
Driving the Analog Inputs
To interface the signal source to the AD7725, at least one op
amp will generally be required. The choice of op amp will be
critical to achieving the full performance of the AD7725. The
op amp not only has to recover from the transient loads that the
ADC imposes on it, but it must also have good distortion char-
acteristics and very low input noise. Resistors in the signal path
will also add to the overall thermal noise floor, necessitating the
choice of low value resistors.
Placing an RC filter between the drive source and the ADC
inputs, as shown in Figure 12, has a number of beneficial
effects: transients on the op amp outputs are significantly
reduced since the external capacitor now supplies the instanta-
neous charge required when the sampling capacitors are switched
to the ADC input pins, and input circuit noise at the sample
images is now significantly attenuated, resulting in improved
overall SNR. The external resistor serves to isolate the external
capacitor from the ADC output, thus improving op amp stabil-
ity while also isolating the op amp output from any remaining
transients on the capacitor. By experimenting with different
filter values, the optimum performance can be achieved for each
application. As a guideline, the RC time constant (R
C) should
be less than a quarter of the clock period to avoid nonlinear
currents from the ADC inputs being stored on the external
capacitor and degrading distortion. This restriction means that
this filter cannot form the main antialias filter for the ADC.
R
C
AD7725
VIN(+)
VIN(鈥�)
Figure 12. Input RC Network
With the unipolar input mode selected, just one op amp is
required to buffer the single-ended input signal to the VIN(+)
input, and a dc input is applied to the VIN(鈥�) pin to provide an
offset. However, driving the AD7725 with differential signals
(i.e., the bipolar input range is selected) has some distinct
advantages: even-order harmonics in both the drive circuits and
the AD7725 front end are attenuated, and the peak-to-peak
input signal range on both inputs is halved. Halving the input
signal range allows some op amps to be powered from the same
supplies as the AD7725. An example of providing differential
drive to the AD7725 is to use a dual op amp.
Dual Op Amp
Although this differential drive circuit will require two op amps
per ADC, it may avoid the need to generate additional supplies
just for these op amps.
Figures 13 and 14 show two circuits for driving the AD7725.
Figure 13 is intended for use when the input signal is biased
about 2.5 V, while Figure 14 is used when the input signal is
biased about ground. While both circuits convert the input
signal into a differential signal, the circuit in Figure 14 also level
shifts the signal so that both outputs are biased about 2.5 V.
Suitable op amps include the AD8047, the AD8041 and its dual
equivalent the AD8042, or the AD8022. The AD8047 has
lower input noise than the AD8041/AD8042 but has to be
supplied from a +7.5 V/鈥�2.5 V supply. The AD8041/AD8042
will typically degrade the SNR from 83 dB to 81 dB but can be
powered from the same single 5 V supply as the AD7725.
220pF
AD7725
VIN(+)
VIN(鈥�)
27
RIN
390
220
10k
10nF
220nF
1 F
27
RSOURCE
AIN =
2V
BIASED
ABOUT +2.5V
REF2
REF1
RFB
220
50
V+
V鈥�
V+
V鈥�
Figure 13. Single-Ended-to-Differential Input Circuit
for Bipolar Mode Operation (Analog Input Biased
about 2.5 V)
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| REC5-4805SRW/H6/C | CONV DC/DC 5W 36-72VIN 05VOUT |
| REC5-4805SRW/H6/A | CONV DC/DC 5W 36-72VIN 05VOUT |
| EVAL-AD7796EBZ | BOARD EVALUATION FOR AD7796 |
| GSM10DRSI-S288 | CONN EDGECARD 20POS .156 EXTEND |
| ECC50DJBN | CONN EDGECARD 100POS .100X.200 |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| EVAL-AD7730EB | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:EVALUATION BOARD I.C. - Bulk |
| EVAL-AD7730EBZ | 鍔熻兘鎻忚堪:BOARD EVAL FOR AD7730 RoHS:鏄� 椤炲垾:绶ㄧ▼鍣�锛岄枊鐧�(f膩)绯荤当(t菕ng) >> 瑭�(p铆ng)浼版澘 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 (ADC) 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:- ADC 鐨勬暩(sh霉)閲�:1 浣嶆暩(sh霉):12 閲囨ǎ鐜囷紙姣忕锛�:94.4k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:USB 杓稿叆鑼冨湇:±VREF/2 鍦ㄤ互涓嬫浠朵笅鐨勯浕婧愶紙妯�(bi膩o)婧�(zh菙n)锛�:- 宸ヤ綔婧害:-40°C ~ 85°C 宸茬敤 IC / 闆朵欢:MAX11645 宸蹭緵鐗╁搧:鏉匡紝杌熶欢 |
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| EVAL-AD7730LEBZ | 鍔熻兘鎻忚堪:BOARD EVALUATION FOR AD7730 RoHS:鏄� 椤炲垾:绶ㄧ▼鍣�锛岄枊鐧�(f膩)绯荤当(t菕ng) >> 瑭�(p铆ng)浼版澘 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 (ADC) 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:- ADC 鐨勬暩(sh霉)閲�:1 浣嶆暩(sh霉):12 閲囨ǎ鐜囷紙姣忕锛�:94.4k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:USB 杓稿叆鑼冨湇:±VREF/2 鍦ㄤ互涓嬫浠朵笅鐨勯浕婧愶紙妯�(bi膩o)婧�(zh菙n)锛�:- 宸ヤ綔婧害:-40°C ~ 85°C 宸茬敤 IC / 闆朵欢:MAX11645 宸蹭緵鐗╁搧:鏉�锛岃粺浠� |
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