參數(shù)資料
型號(hào)： EVAL-AD7710EB
廠商： Analog Devices, Inc.
英文描述： CAPACITOR 0.1UF CERAMIC 0805
中文描述： ADC的信號(hào)調(diào)理
文件頁(yè)數(shù)： 20/28頁(yè)
文件大?。?/td> 220K
代理商： EVAL-AD7710EB
REV. F
–20–
AD7710
Read Operation
Data can be read from either the output register, the control
register or the calibration registers. A0 determines whether the
data read accesses data from the control register or from the
output/calibration registers. This A0 signal must remain valid
for the duration of the serial read operation. With A0 high, data
is accessed from either the output register or from the calibra-
tion registers. With A0 low, data is accessed from the control
register.
The function of the
DRDY
line is dependent only on the output
update rate of the device and the reading of the output data
register.
DRDY
goes low when a new data word is available in
the output data register. It is reset high when the last bit of data
(either 16th bit or 24th bit) is read from the output register. If
data is not read from the output register, the
DRDY
line will
remain low. The output register will continue to be updated at
the output update rate but
DRDY
will not indicate this. A read
from the device in this circumstance will access the most recent
word in the output register. If a new data word becomes avail-
able to the output register while data is being read from the
output register,
DRDY
will not indicate this and the new data
word will be lost to the user.
DRDY
is not affected by reading
from the control register or the calibration registers.
Data can only be accessed from the output data register when
DRDY
is low. If
RFS
goes low with
DRDY
high, no data trans-
fer will take place.
DRDY
does not have any effect on reading
data from the control register or from the calibration registers.
Figure 10 shows a timing diagram for reading from the AD7710
in the self-clocking mode. This read operation shows a read
from the AD7710’s output data register. A read from the con-
trol register or calibration registers is similar but in these cases
the
DRDY
line is not related to the read function. Depending
on the output update rate, it can go low at any stage in the con-
trol/calibration register read cycle without affecting the read and
its status should be ignored. A read operation from either the
control or calibration registers must always read 24 bits of data
from the respective register.
Figure 10 shows a read operation from the AD7710. For the
timing diagram shown, it is assumed that there is a pull-up
resistor on the SCLK output. With
DRDY
low, the
RFS
input
is brought low.
RFS
going low enables the serial clock of the
AD7710 and also places the MSB of the word on the serial data
line. All subsequent data bits are clocked out on a high to low
transition of the serial clock and are valid prior to the following
rising edge of this clock. The final active falling edge of SCLK
clocks out the LSB and this LSB is valid prior to the final active
rising edge of SCLK. Coincident with the next falling edge of
SCLK,
DRDY
is reset high.
DRDY
going high turns off the
SCLK and the SDATA outputs. This means that the data hold
time for the LSB is slightly shorter than for all other bits.
SDATA (O)
SCLK (O)
THREE-STATE
RFS (I)
A0 (I)
t
4
t
5
t
7
t
8
t
10
9
t
DRDY (O)
t
6
t
3
MSB
LSB
t
2
Figure 10. Self-Clocking Mode, Output Data Read Operation
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