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參數(shù)資料
| 型號： | EVAL-AD767XCB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Evaluation Board AD766X/AD767X |
| 中文描述： | 評估板AD766X/AD767X |
| 文件頁數(shù)： | 4/15頁 |
| 文件大小： | 1841K |
| 代理商： | EVAL-AD767XCB |
REV. PrK
EVAL-AD766XCB/AD767XCB
–4–
PRELIMINARY TECHNICAL DATA
Table III. EVAL-AD766XCB/AD767XCB Test Points
Test Point
Available Signal
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
DGND Digital ground
DGND Digital ground
SIG+
ADC Analog input
AGND Analog ground close to SIG+
REF
ADC Reference input
BUSY
ADC BUSY signal
ADC
signal
ADC
signal
AGND Analog ground close to REF
ADC
F
SYNC
MCLK divided by 2
OVDD ADC digital output supply
DVDD ADC digital core supply
VANA1 ADC analog supply
AGND Analog ground close to SIG-
SIG-
ADC Analog input
signal
Table IV. Component values Vs. Input ranges ( AD7660 )
Input range
R1
R3
R6
R7
± 10V
± 5V
0 to -5V
8k 1k
8k 2k
8k 8k
8k
6.67k
0
10k
10k
none
Table V. Component values Vs. Input ranges ( AD7664 )
Input range
R1
R3
R6
R7
± 10V
± 5V
0 to -5V
2k 250
2k 500
1k 1k
8k
6.67k
0
10k
10k
none
Jumper
Designation with the control
board ( Factory
settings)
Default position
Function
TABLE II. JUMPER DESCRIPTION
JP13
A, U3 side
Selection of IMPULSE. When the button of the switch is close to J4 connector
( not A position ), the ADC uses the IMPULSE mode which is the mode with the
lowest power dissipation. With the AD7660, JP13 is a spare switch.
JP14
A, U3 side
TEST1. For factory use only and it is pull down.
JP15
A, U3 side
TEST0. For factory use only and it is pull down.
JP16
A, U3 side
Selection of EXT/
the switch is close to J4 connector ( not A position ) and when the serial reading
mode is selected, the data are read with an external serial clock SCLK generated from
the master clock MCLK otherwise the data are read with the ADC serial clock. When
external serial clock reading mode is selected, MCLK has to be fast enough to be able
the read the data properly as explained in the AD766X data sheet. JP16 has no use in
parallel reading mode.
( use of external or internal serial clock ). When the button of
JP17
A, U3 side
Selection of INVSYNC ( SYNC active level ). When the button of the switch is close
to J4 connector ( not A position ) and when the master serial reading mode is se
lected, the SYNC signal is active Low. JP17 has no use in parallel reading mode or
slave serial reading mode.
JP18
A, U3 side
Selection of INVSCLK ( SCLK active edge ). When the button of the switch is close
to J4 connector ( not A position ) and when the serial reading mode is selected,
INVSCLK is high. JP18 has no use in parallel reading mode.
JP19
not A
Selection of
otherwise the on-board
the on-board
signal. When JP19 is in position A, the signal on J3 is used
generation is used. MCLK signal is used to generate
signal.
JP20
not A
Selection of REF signal. When JP20 is in position A, the REF is buffered. When
JP20 is not in position A, the REF is not buffered.
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