參數(shù)資料
型號(hào)： EVAL-AD7657-1EDZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 16/32頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL CONTROL AD7657-1
標(biāo)準(zhǔn)包裝： 1
系列： iCMOS®
ADC 的數(shù)量： 6
位數(shù)： 14
采樣率（每秒）： 250k
數(shù)據(jù)接口： 串行，并聯(lián)
輸入范圍： ±10 V
在以下條件下的電源（標(biāo)準(zhǔn)）： 140mW @ 250kSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7657-1
已供物品： 板
相關(guān)產(chǎn)品： AD7657YSTZ-1-RL-ND - IC ADC 14BIT 6CH 250KSPS 64LQFP
AD7657YSTZ-1-ND - IC ADC 14BIT 6CH 250KSPS 64LQFP
AD7657BSTZ-1-RL-ND - IC ADC 14BIT 6CH 250KSPS 64LQFP
AD7657BSTZ-1-ND - IC ADC 14BIT 6CH 250KSPS 64LQFP
AD7657YSTZ-REEL-ND - IC ADC 14BIT 6CH 250KSPS 64LQFP
AD7657YSTZ-ND - IC ADC 14BIT 6CH 250KSPS 64LQFP
AD7657BSTZ-ND - IC ADC 14BIT 6CH 250KSPS 64-LQFP
AD7657BSTZ-REEL-ND - IC ADC 14BIT 6CH 250KSPS 64-LQFP
Data Sheet
AD7656-1/AD7657-1/AD7658-1
Rev. D | Page 23 of 32
further CONVST rising edges on any of the CONVST pins are
ignored while BUSY is high.
Data can be read from the AD7656-1/AD7657-1/AD7658-1 via
the parallel data bus with standard CS and RD signals (W/B = 0).
To read the data over the parallel bus, tie SER/PAR SEL low. The
CS and RD input signals are internally gated to enable the
conversion result onto the data bus. The data lines DB0 to DB15
leave their high impedance state when both CS and RD are
logic low.
The CS signal can be permanently tied low, and the RD signal
can be used to access the conversion results. A read operation
can take place after the BUSY signal goes low. The number of
required read operations depends on the number of ADCs that
are simultaneously sampled (see Figure 29). If CONVST A
and CONVST B are simultaneously brought low, four read
operations are required to obtain the conversion results from
V1, V2, V3, and V4. If CONVST A and CONVST C are
simultaneously brought low, four read operations are required
to obtain the conversion results from V1, V2, V5, and V6.
The conversion results are output in ascending order. For
the AD7657-1, DB15 and DB14 contain two leading 0s, and
DB[13:0] output the 14-bit conversion result. For the AD7658-1,
DB[15:12] contain four leading 0s, and DB[11:0] output the
12-bit conversion result.
When using the three CONVST signals to independently
initiate conversions on the three ADC pairs, once a rising edge
occurs on any one CONVST pin to initiate a conversion then any
further CONVST rising edges on any of the CONVST pins are
ignored while BUSY is high.
Although a conversion can be initiated during a read sequence,
it is not recommended practice, because doing so may affect the
performance of the conversion. For the specified performance,
it is recommended to perform the read after the conversion.
For unused input channel pairs, tie the associated CONVST pin
to VDRIVE.
If there is only an 8-bit bus available, the AD7656-1/AD7657-1/
AD7658-1 parallel interface can be configured to operate in byte
mode (W/B = 1). In this configuration, the DB7/HBEN/DCEN
pin takes on its HBEN function. Each channel conversion result
from the AD7656-1/AD7657-1/AD7658-1 can be accessed in
two read operations, with eight bits of data provided on DB15
to DB8 for each of the read operations (see Figure 30). The
HBEN pin determines whether the read operation first accesses
the high byte or the low byte of the 16-bit conversion result. To
always access the low byte first on DB15 to DB8, tie the HBEN
pin low. To always access the high byte first on DB15 to DB8, tie
the HBEN pin high. In byte mode when all three CONVST pins
are pulsed together to initiate simultaneous conversions on all six
ADCs, 12 read operations are necessary to read back the six
16-/14-/12-bit conversion results. DB[6:0] should be left
unconnected in byte mode.
V1
V2
V3
V4
V5
V6
CONVST A,
CONVST B,
CONVST C
BUSY
CS
RD
DATA
tQUIET
t7
t8
t9
t4
t2
t3
t5
t6
tACQ
tCONV
t10
07017-
027
Figure 29. Parallel Interface Timing Diagram (W/B = 0)
LOW BYTE
HIGH BYTE
DB15 TO DB8
CS
RD
t3
t6
t7
t8
t4
t5
t9
07017-
028
Figure 30. Parallel Interface—Read Cycle for Byte Mode of Operation (W/B = 1, HBEN = 0)
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