參數(shù)資料
型號: EVAL-AD7476ACBZ
廠商: Analog Devices Inc
文件頁數(shù): 10/29頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD7476A
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 1
位數(shù): 12
采樣率(每秒): 1M
數(shù)據(jù)接口: 串行
輸入范圍: 0 ~ 5.25 V
在以下條件下的電源(標(biāo)準(zhǔn)): 17.5mW @ 1MSPS,5 V
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD7476A
已供物品: 板,CD
相關(guān)產(chǎn)品: AD7476ARTZ-500RL7DKR-ND - IC ADC 12BIT 1MSPS SOT-23-6
AD7476ABKSZREELDKR-ND - IC ADC 12BIT 1MSPS SC70-6
AD7476BRTZ-R2TR-ND - IC ADC 12BIT 1MSPS SOT23-6
AD7476ARTZ-REEL7-ND - IC ADC 12BIT 1MSPS LP SOT23-6
AD7476ABKSZ-500RL7-ND - IC ADC 12BIT 1MSPS LP SC70-6
AD7476AAKSZ-REEL7-ND - IC ADC 12BIT 1MSPS LP SC70-6
AD7476AAKSZ-500RL7TR-ND - IC ADC 12BIT 1MSPS LP SC70-6
AD7476AYRMZ-REEL7-ND - IC ADC 12BIT 1MSPS LP 8MSOP
AD7476AAKSZ-REEL-ND - IC ADC 12BIT 1MSPS LP SC70-6
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更多...
AD7476A/AD7477A/AD7478A
Rev. F | Page 17 of 28
Table 8 provides typical performance data with various op amps
used as the input buffer for a 100 kHz input tone at room
temperature under the same setup conditions.
Table 8. AD7476A Typical Performance with Various Input
Buffers, VDD = 3 V
Op Amp in the Input Buffer
AD7476A SNR Performance (dB)
72.3
72.5
71.4
When no amplifier is used to drive the analog input, limit the
source impedance to low values. The maximum source imped-
ance depends on the amount of total harmonic distortion (THD)
that can be tolerated. The THD increases as the source impedance
increases, degrading the performance (see Figure 13).
DIGITAL INPUTS
The digital inputs applied to the AD7476A/AD7477A/AD7478A
are not limited by the maximum ratings that limit the analog
input. Instead, the digital inputs applied can reach 7 V and are
not restricted by the VDD + 0.3 V limit as on the analog input.
For example, if operating the AD7476A/AD7477A/AD7478A
with a VDD of 3 V, use 5 V logic levels on the digital inputs.
However, note that the data output on SDATA still has 3 V logic
levels when VDD = 3 V. Another advantage of SCLK and CS not
being restricted by the VDD + 0.3 V limit is that power supply
sequencing issues are avoided. If CS or SCLK are applied before
VDD, there is no risk of latch-up as there would be on the analog
input if a signal greater than 0.3 V were applied prior to VDD.
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