
AD7466/AD7467/AD7468
a
Prelimnary Technical Data
REV. PrC 07/01
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Analog Devices, Inc., 2001
1.8 V Mcro-Power,
8/10/12-Bit ADCs in 6 Lead SOT-23
F UNC T IONA L BL OC K D IA GR A M
FEATURES
Specified for V
DD
of 1.8 V to 3.6 V
Low Power:
0.9 mW max at 60 kSPS with 3.6 V Supplies
0.4 mW max at 100 kSPS with 1.8 V Supplies
Fast Throughput Rate: 100 kSPS
Wide Input Bandwidth:
70dB SNR at 30 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface
SPI/QSPI/
μ
Wire/DSP Compatible
Standby Mode: 0.5
μ
A max
6-Lead SOT-23 Package and 8 lead
μ
SOIC
APPLICATIONS
Battery Powered Systems
Medical Instruments
Ramote Data Acquisition
Isolated Data Acquisition
G E NE R A L D E SC R IP T ION
T he AD7466/AD7467/AD7468 are 12/10/8-bit, high
speed, low power, successive-approximation ADCs re-
spectively. T he parts operate from a single 1.8 V to 3.6 V
power supply and feature throughput rates up to 100
kSPS. T he parts contain a low-noise, wide bandwidth
track/hold amplifier which can handle input frequencies in
excess of 100 kHz.
T he conversion process and data acquisition are controlled
using
CS
and the serial clock, allowing the devices to
interface with microprocessors or DSPs. T he input signal
is sampled on the falling edge of
CS
and the conversion is
also initiated at this point. T here are no pipelined delays
associated with the part.
T he AD7466/AD7467/AD7468 use advanced design tech-
niques to achieve very low power dissipation at high
throughput rates.
T he reference for the part is taken internally from V
DD.
T his allows the widest dynamic input range to the ADC.
T hus the analog input range for the part is 0 to V
DD
. T he
conversion rate is determined by the SCLK .
P R OD UC T H IG H L IG H T S
1. Specified for Supply voltages of 1.8 V to 3.6 V
2. 8/10/12-Bit ADCs in a SOT -23 package.
3. High T hroughput with Low Power Consumption
4. Flexible Power/Serial Clock Speed Management
T he conversion rate is determined by the serial clock
allowing the conversion time to be reduced through the
serial clock speed increase. Automatic power down after
conversion, which allows the average power cunsumption
to be reduced when in powerdown. Power consumption
is 0.5
μ
A max when in powerdown.
5. Reference derived from the power supply.
6. No Pipeline Delay
T he part features a standard successive-approximation
ADC with accurate control of the conversions via a
CS
input.
T/H
VIN
AD7466/67/68
VDD
12/10/8-BIT
SUCCESSIVE
APPROXIMATION
ADC
SCLK
CONTROL LOGIC
SDATA
CS
GND
pecifications