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參數(shù)資料
| 型號： | EVAL-AD7276SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7276 |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 3M |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 0 ~ 3.6 V |
| 在以下條件下的電源（標準）： | 19.8mW @ 3MSPS，3.6 V |
| 工作溫度： | -40°C ~ 125°C |
| 已用 IC / 零件： | AD7276 |
| 已供物品： | 板 |
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AD7276/AD7277/AD7278
Rev. C | Page 18 of 28
CS can idle high until the next conversion or low until CS returns
high before the next conversion (effectively idling CS low).
MODES OF OPERATION
The mode of operation of the AD7276/AD7277/AD7278 is
selected by controlling the logic state of the CS signal during a
conversion. There are three possible modes of operation: normal
mode, partial power-down mode, and full power-down mode.
The point at which CS is pulled high after the conversion has
been initiated determines which power-down mode, if any, the
device enters. Similarly, if the device is already in power-down
mode, CS can control whether the device returns to normal
operation or remains in power-down mode. These modes of
operation are designed to provide flexible power management
options, which can be chosen to optimize the power dissipation/
throughput rate ratio for different application requirements.
Once a data transfer is complete (SDATA has returned to three-
state), another conversion can be initiated after the quiet time,
tQUIET, has elapsed by bringing CS low again.
Partial Power-Down Mode
This mode is intended for use in applications where slower
throughput rates are required. An example of this is when either
the ADC is powered down between each conversion or a series
of conversions is performed at a high throughput rate and then
the ADC is powered down for a relatively long duration between
these bursts of several conversions. When the AD7276/AD7277/
AD7278 are in partial power-down mode, all analog circuitry is
powered down except the bias-generation circuit.
Normal Mode
This mode is intended for fastest throughput rate performance
because the device remains fully powered at all times, eliminating
worry about power-up times. Figure 24 shows the general diagram
of AD7276/AD7277/AD7278 operation in this mode.
To enter partial power-down mode, interrupt the conversion
process by bringing CS high between the second and 10th falling
edges of SCLK, as shown in
.
Once CS is brought high in this window of SCLKs, the part
enters partial power-down mode, the conversion that was
initiated by the falling edge of CS is terminated, and SDATA
goes back into three-state. If CS is brought high before the
second SCLK falling edge, the part remains in normal mode and
does not power down. This prevents accidental power-down due
to glitches on the CS line.
The conversion is initiated on the falling edge of CS as described
in the
section. To ensure that the part remains
fully powered up at all times,
CS must remain low until at least
10 SCLK falling edges elapse after the falling edge of CS. If CS is
brought high after the 10th SCLK falling edge but before the 16th
SCLK falling edge, the part remains powered up, but the con-
version is terminated and SDATA goes back into three-state.
For the AD7276, a minimum of 14 serial clock cycles are required
to complete the conversion and access the complete conversion
result. For the AD7277 and AD7278, a minimum of 12 and
10 serial clock cycles are required to complete the conversion
and to access the complete conversion result, respectively.
CS
SCLK
110
12
14
16
AD7276/
AD7677/AD7278
SDATA
VALID DATA
04
90
3-
02
4
Figure 24. Normal Mode Operation
SCLK
12
10
16
SDATA
THREE-STATE
CS
04
90
3-
0
25
Figure 25. Entering Partial Power-Down Mode
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