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參數(shù)資料
| 型號(hào)： | EVAL-AD5535EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD5535 |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| DAC 的數(shù)量： | 32 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 1.2M |
| 數(shù)據(jù)接口： | 串行 |
| 設(shè)置時(shí)間： | 65µs |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | AD5535 |
| 相關(guān)產(chǎn)品： | AD5535ABCZ-ND - IC DAC 14BIT 32CHAN 124CSPBGA |
AD5535
Rev. A | Page 13 of 16
Figure 17 shows the connection diagram.
AD5535-to-PIC16C6x/7x Interface
*ADDITIONAL PINS OMITTED FOR CLARITY
AD5535*
ADSP-2101/
ADSP-2103*
SCLK
DIN
SYNC
SCLK
DT
TFS
05068-011
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit = 0. This is done
by writing to the synchronous serial port control register
(SSPCON). See the PIC16/17 Microcontroller User Manual.
In this example, I/O port RA1 is being used to pulse SYNC
and enable the serial port of the AD5535. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, three consecutive write operations are
necessary to transmit 19 bits of data. Data is transmitted MSB
first. It is important to left justify the data in the SPDR register
so that the first 19 bits transmitted contain valid data. RA1 must
be pulled low to start a transfer. It must be brought high and
pulled low again before any further write cycles can take place.
Figure 17. AD5535-to-ADSP-2101/ADSP-2103 Interface
AD5535-to-MC68HC11 Interface
The serial peripheral interface (SPI) on the MC68HC11 is
configured for master mode (MSTR = 1), clock polarity bit
(CPOL) = 0, and clock phase bit (CPHA) = 1. The SPI is
configured by writing to the SPI control register (SPCR)—see
the 68HC11 User Manual. SCK of the MC68HC11 drives the
SCLK of the AD5535 and the MOSI output drives the serial
data line (D
Figure 19 shows the connection diagram.
*ADDITIONAL PINS OMITTED FOR CLARITY
AD5535*
PIC16C6x/7x*
SCLK
DIN
SYNC
SCK/RC3
SDI/RC4
RA1
05068-013
) of the AD5535. The SYNC
IN
signal is derived from
a port line (PC7). When data is being transmitted to the
AD5535, the SYNC line is taken low (PC7).
Data appearing on the MOSI output is valid on the falling edge
of SCK. The MC68HC11 transfers only eight bits of data during
each serial transfer operation; therefore, three consecutive write
operations are necessary to transmit 19 bits of data. Data is
transmitted MSB first. It is important to left justify the data in
the SPDR register so that the first 19 bits transmitted contain
valid data. PC7 must be pulled low to start a transfer. It is taken
high and pulled low again before any further write cycles can
take place. See
Figure 19. AD5535-to-PIC16C6x/7x Interface
AD5535-to-8051 Interface
The AD5535 requires a clock synchronized to the serial data. The
8051 serial interface must therefore be operated in Mode 0. In
this mode, serial data exits the 8051 through R×D, and a shift
clock is output upon T×D. The SYNC signal is derived from a
port line (P1.1).
Figure 20 shows how the 8051 is connected to
the AD5535. Because the AD5535 shifts data out upon the rising
edge of the shift clock and latches data in upon the falling edge,
the shift clock must be inverted. Note also that the AD5535
requires its data with the MSB first. Because the 8051 outputs the
LSB first, the transmit routine must take this into account.
*ADDITIONAL PINS OMITTED FOR CLARITY
AD5535*
MC68HC11*
SCLK
DIN
SYNC
SCK
MOSI
PC7
05068-012
*ADDITIONAL PINS OMITTED FOR CLARITY
AD5535*
8051*
SCLK
DIN
SYNC
TxD
RxD
P1.1
05068-014
Figure 18. AD5535-to-MC68HC11 Interface
Figure 20. AD5535-to-8051 Interface
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