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參數(shù)資料
| 型號： | EVAL-AD5520EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Per Pin Parametric Measurement Unit/Source Measure Unit |
| 中文描述： | 每個引腳參數(shù)測量單元/源測量單元 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 763K |
| 代理商： | EVAL-AD5520EB |
REV. A
–14–
AD5520
Figure 7 illustrates the transfer function of the current force mode.
I
DUT
V
CLH
R
DUT
V
CLL
R
DUT
V
CLH
V
CLH
V
DUT
V
CLH
V
CLH
V
FIN
V
FIN
Figure 7. Current Force Transfer Function
Measure Voltage
A DUT voltage is tested via the voltage measure amplifier by a
window comparator to ensure that CPH and CPL levels are not
exceeded. In addition, the DUT voltage is automatically tested
against the voltage levels at the clamp, and clamp flags are
enabled if the DUT voltage exceeds either of the levels.
Short Circuit Protection
The AD5520 is designed to withstand a direct short circuit on
any of the amplifier outputs.
SETTLING TIME CONSIDERATIONS
Fast throughput is a key requirement in automatic test equipment
because it relates directly to the cost of manufacturing the DUT,
thus reducing the time required to make a DAC measurement is of
upmost importance. When taking measurements using a PMU, the
limiting factor is usually the time it takes the output to settle to the
required accuracy so a measurement can be taken. DUT capaci-
tance, measurement accuracy, and the design of the PMU are the
major contributors to this time. Figure 8 shows a simplified block
diagram of the AD5520 PMU. In brief, the device consists of a
force control amplifier, access to a number of selectable sense
resistors, a voltage measure instrumentation amplifier, and a
current measure instrumentation amplifier. To optimize the
performance of the device, there are also nodes provided where
external compensation capacitors are added. As mentioned, mak-
ing an accurate measurement in the fastest time while avoiding
overshoots and ringing is the key requirement in any ATE system.
This in itself provides challenges. The external compensation
capacitors set up different settling times or bandwidths on the force
control amplifier, and, while one compensation capacitor value
may suit one range, it may not suit other ranges. To optimize
measurement performance and speed, differences in signal behav-
ior on each range and frequency of use of each range need to be
taken into account.
When selecting a faster settling time, there is a trade-off between
the faster settling, overshoots, and ringing. A small compensa-
tion value will result in faster settling but may incur penalties in
overshoots or ringing at the DUT. Compensation capacitor
selection should be optimized to ensure minimum overshoots
while still giving good settling time performance.
While careful selection of the compensation capacitor is required
to minimize the settling time, another factor can greatly contribute
to the overall settling of the loop if the feedback loop is broken
in some manner and the force control amplifier goes to either
the positive or negative rails. There is a finite amount of time
required for the amplifier to recover from this condition, typi-
cally 85
μ
s, which adds to the settling of the loop. Ensuring that
the force control amplifier never goes into saturation is the best
solution. This solution can be helped by putting the device into
standby mode at any time the operating mode or range selection
is changed. In addition, ensure that the selected output range
can supply the required current needed by the DUT.
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration
to the power supply and the ground return layout helps to ensure
the rated performance. The printed circuit board on which
the AD5520 is mounted should be designed so that the analog
and digital sections are separated and confined to certain areas
of the board. If the PMU is in a system where multiple devices
require an AGND-to-DGND connection, the connection should
be made at one point only. The star ground point should be
established as close as possible to the device.
This PMU should have ample supply bypassing of 10
μ
F in
parallel with 0.1
μ
F on the supply located as close to the pack-
age as possible, ideally right up against the device. The 0.1
μ
F
capacitor should have low effective series resistance (ESR) and
effective series inductance (ESI), such as the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching. Low ESR, 1
μ
F to 10
μ
F, tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
Fast switching signals, such as clocks, should be shielded with
digital ground to avoid radiating noise to other parts of the
board and should never be run near the reference inputs.
Avoid crossover of digital and analog signals. Traces on oppo-
site sides of the board should run at right angles to each other.
This reduces the effects of feedthrough through the board. A
microstrip technique is by far the best but not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to the ground plane while signal
traces are placed on the solder side.
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