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參數(shù)資料
| 型號： | EVAL-AD5516-3EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/16頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION AD5516 |
| 產(chǎn)品培訓模塊： | DAC Architectures |
| 標準包裝： | 1 |
| DAC 的數(shù)量： | 16 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 750k |
| 數(shù)據(jù)接口： | 串行 |
| 設(shè)置時間： | 32µs |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD5516-3 |
| 相關(guān)產(chǎn)品： | AD5516ABCZ-3-ND - IC DAC 12BIT 16CH BIPO 74-CSPBGA AD5516ABCZ-2-ND - IC DAC 12BIT VOUT 16CH 74-CSPBGA AD5516ABC-3-ND - IC DAC 12BIT 16CH 74-CSPBGA AD5516ABC-2-ND - IC DAC 12BIT 16CH 74-CSPBGA AD5516ABC-1-ND - IC DAC 12BIT 16CH 74-CSPBGA |
REV. B
AD5516
–7–
TERMINOLOGY
Integral Nonlinearity (INL)
This is a measure of the maximum deviation from a straight line
passing through the endpoints of the DAC transfer function. It is
expressed in LSBs.
Differential Nonlinearity (DNL)
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified DNL of –1 LSB maximum ensures
monotonicity.
Bipolar Zero Error
Bipolar zero error is the deviation of the DAC output from the ideal
midscale of 0 V. It is measured with 10...00 loaded to the DAC.
It is expressed in LSBs.
Positive Full-Scale Error
This is the error in the DAC output voltage with all 1s loaded to
the DAC. Ideally the DAC output voltage, with all 1s loaded to the
DAC registers, should be 2.5 V – 1 LSB (AD5516-1), 5 V – 1 LSB
(AD5516-2), and 10 V – 1 LSB (AD5516-3). It is expressed in LSBs.
Negative Full-Scale Error
This is the error in the DAC output voltage with all 0s loaded to
the DAC. Ideally the DAC output voltage, with all 0s loaded to the
DAC registers, should be –2.5 V (AD5516-1), –5 V (AD5516-2),
and –10 V (AD5516-3). It is expressed in LSBs.
Output Temperature Coefficient
This is a measure of the change in analog output with changes in
temperature. It is expressed in ppm/
∞C of FSR.
DC Power Supply Rejection Ratio
DC power supply rejection ratio (PSRR) is a measure of the change
in analog output for a change in supply voltage (VDD and VSS).
It is expressed in dB. VDD and VSS are varied
±5%.
DC Crosstalk
This is the dc change in the output level of one DAC at midscale
in response to a full-scale code change (all 0s to all 1s and vice
versa) and output change of another DAC. It is expressed in LSB.
Output Settling Time
This is the time taken from when the last data bit is clocked into
the DAC until the output has settled to within
±0.5 LSB of its
final value (see TPC 7).
Digital-to-Analog Glitch Impulse
This is the area of the glitch injected into the analog output when
the code in the DAC register changes state. It is specified as the
area of the glitch in nV-s when the digital code is changed by
1 LSB at the major carry transition (011...11 to 100...00 or
100...00 to 011...11).
Digital Crosstalk
This is the glitch impulse transferred to the output of one DAC at
midscale while a full-scale code change (all 1s to all 0s and vice
versa) is being written to another DAC. It is expressed in nV-s.
Analog Crosstalk
This is the area of the glitch transferred to the output (VOUT) of
one DAC due to a full-scale change in the output (VOUT) of
another DAC. The area of the glitch is expressed in nV-s.
Digital Feedthrough
This is a measure of the impulse injected into the analog outputs
from the digital control inputs when the part is not being written
to, i.e., SYNC is high. It is specified in nV-s and measured with
a worst-case change on the digital input pins, e.g., from all 0s to
all 1s and vice versa.
Output Noise Spectral Density
This is a measure of internally generated random noise. Random
noise is characterized as a spectral density (voltage per root hertz).
It is measured in nV/(Hz)
1/2.
PIN FUNCTION DESCRIPTIONS (continued)
Mnemonic
Function
SCLK
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock
speeds up to 20 MHz.
DIN
Serial Data Input. Data must be valid on the falling edge of SCLK.
DOUT
Serial Data Output. DOUT can be used for daisy-chaining a number of devices together or for reading back the
data in the shift register for diagnostic purposes. Data is clocked out on DOUT on the rising edge of SCLK and is
valid on the falling edge of SCLK.
DCEN
1
Active High Control Input. This pin is tied high to enable Daisy-Chain Mode.
RESET2
Active Low Control Input. This resets all DAC registers to power-on value.
PD
1
Active High Control Input. All DACs go into power-down mode when this pin is high. The DAC outputs go into
a high impedance state.
BUSY
Active Low Output. This signal tells the user that the analog calibration loop is active. It goes low during conversion.
The duration of the pulse on
BUSY determines the maximum DAC update rate, f
UPDATE. Further writes to the
AD5516 are ignored while
BUSY is active.
NOTES
1Internal pull-down device on this logic input. Therefore it can be left floating and will default to a logic low condition.
2Internal pull-up device on this logic input. Therefore it can be left floating and will default to a logic high condition.
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