參數(shù)資料
型號(hào)： EVAL-AD5379EB
廠商： Analog Devices, Inc.
元件分類(lèi)： 串行DAC
英文描述： 40-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage-Output DAC
中文描述： 40通道，14位，并行和串行輸入，雙極性電壓輸出DAC
文件頁(yè)數(shù)： 22/28頁(yè)
文件大小： 393K
代理商： EVAL-AD5379EB
AD5379
INTERFACES
The AD5379 contains a parallel and a serial interface. The active
interface is selected via the SER/PAR pin.
Rev. 0 | Page 22 of 28
The AD5379 uses an internal FIFO memory to allow high speed
successive writes in both serial and parallel mode. The user can
continue writing new data to the AD5379 while write instruc-
tions are being executed. The BUSY signal goes low while
instructions in the FIFO are being executed. Up to 120 succes-
sive instructions can be written to the FIFO at maximum speed.
When the FIFO is full, additional writes to the AD5379 are
ignored.
To minimize both the power consumption of the device and
on-chip digital noise, the active interface powers up fully only
when the device is being written to, that is, on the falling edge of
WR or on the falling edge of SYNC.
All digital interfaces are 2.5 V LVTTL compatible when
operating from a 2.7 V to 3.6 V V
CC
supply.
PARALLEL INTERFACE
A pull-down on the SER/PAR pin makes the parallel interface
the default. If using the parallel interface, the SER/PAR pin can
be left unconnected. Figure 6 shows the timing diagram for a
parallel write to the AD5379. The parallel interface is controlled
by the following pins.
CS Pin
Active low device select pin.
WR Pin
On the rising edge of WR, with CS low, the address values at
Pins A7 to A0 are latched and data values at Pins DB13 to DB0
are loaded into the selected AD5379 input registers.
REG1, REG0 Pins
The REG1 and REG0 pins determine the destination register of
the data being written to the AD5379. See Table 11.
Table 11. Register Selection
REG1
REG0
Register Selected
1
1
Input Data Register (x1)
1
0
Offset Register (c)
0
1
Gain Register (m)
0
0
Special Function Register
DB13 to DB0 Pins
The AD5379 accepts a straight 14-bit parallel word on DB0 to
DB13, where DB13 is the MSB and DB0 is the LSB. See Table 12,
Table 13, Table 14, Table 15, and Table 16.
A7 to A0 Pins
Each of the 40 DAC channels can be addressed individually. In
addition, several channel groupings enable the user to simulta-
neously write the same data to multiple DAC channels. Address
Bits A7 to A4 are decoded to select one group or multiple
groups of registers. Address Bits A3 to A0 select one of ten input
data registers (x1), offset registers (c), or gain registers (m). See
Table 17.
SERIAL INTERFACE
The SER/PAR pin must be tied high to enable the serial inter-
face and disable the parallel interface. The serial interface is
controlled by five pins, as follows.
SYNC, DIN, SCLK
Standard 3-wire interface pins.
DCEN
Selects standalone mode or daisy-chain mode.
SDO
Data out pin for daisy-chain mode.
Figure 4 and Figure 5 show the timing diagrams for a serial
write to the AD5379 in standalone and daisy-chain modes,
respectively.
The 24-bit data word format for the serial interface is shown in
Figure 21.
MSB
REG0
DB13–DB0
LSB
A7–A0
REG1
REGISTER DATA BITS
GROUP/CHANNEL
SELECT BITS
REGISTER SELECT
BITS
0
Figure 21. Serial Data Format
Standalone Mode
By connecting the DCEN (daisy-chain enable) pin low,
standalone mode is enabled. The serial interface works with
both a continuous and a burst serial clock. The first falling edge
of SYNC starts the write cycle and resets a counter that counts
the number of serial clocks to ensure that the correct number of
bits is shifted into the serial shift register. Additional edges on
SYNC are ignored until 24 bits are shifted in. Once 24 bits are
shifted in, the SCLK is ignored. In order for another serial
transfer to take place, the counter must be reset by the falling
edge of SYNC.
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