DVCC = 2.5 V to 5.5 V; V
參數(shù)資料
型號(hào)： EVAL-AD5373EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 27/29頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD5373
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 32
位數(shù)： 14
采樣率（每秒）： 540k
數(shù)據(jù)接口： 串行
設(shè)置時(shí)間： 20µs
DAC 型： 電壓
工作溫度： -40°C ~ 85°C
已供物品： 板，CD
已用 IC / 零件： AD5373
AD5372/AD5373
Rev. C | Page 6 of 28
TIMING CHARACTERISTICS
DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = 16.5 V to 8 V; VREFx = 3 V; AGND = DGND = SIGGNDx = 0 V; CL = 200 pF to GND;
RL = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted.
Table 4. SPI Interface
Parameter 1, 2, 3
Limit at TMIN, TMAX
Unit
Description
t1
20
ns min
SCLK cycle time
t2
8
ns min
SCLK high time
t3
8
ns min
SCLK low time
t4
11
ns min
SYNC falling edge to SCLK falling edge setup time
t5
20
ns min
Minimum SYNC high time
t6
10
ns min
24th SCLK falling edge to SYNC rising edge
t7
5
ns min
Data setup time
t8
5
ns min
Data hold time
t94
42
ns max
SYNC rising edge to BUSY falling edge
t10
1/1.5
μs typ/μs max
BUSY pulse width low (single-channel update); see Table 9
t11
600
ns max
Single-channel update cycle time
t12
20
ns min
SYNC rising edge to LDAC falling edge
t13
10
ns min
LDAC pulse width low
t14
3
μs max
BUSY rising edge to DAC output response time
t15
0
ns min
BUSY rising edge to LDAC falling edge
t16
3
μs max
LDAC falling edge to DAC output response time
t17
20/30
μs typ/μs max
DAC output settling time
t18
140
ns max
CLR/RESET pulse activation time
t19
30
ns min
RESET pulse width low
t20
400
μs max
RESET time indicated by BUSY low
t21
270
ns min
Minimum SYNC high time in readback mode
t225
25
ns max
SCLK rising edge to SDO valid
t23
80
ns max
RESET rising edge to BUSY falling edge
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
4 t9 is measured with the load circuit shown in Figure 2.
5 t22 is measured with the load circuit shown in Figure 3.
TO
OUTPUT
PIN
CL
50pF
RL
2.2k
VOL
DVCC
05
81
5-
00
2
VOH (MIN) – VOL (MAX)
2
200A
IOL
200A
IOH
TO OUTPUT
PIN
CL
50pF
0
581
5-
0
03
Figure 2. Load Circuit for BUSY Timing Diagram
Figure 3. Load Circuit for SDO Timing Diagram
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