DVCC = 2.5 V to 5.5 V; V
參數(shù)資料
型號(hào)： EVAL-AD5371EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 27/29頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD5371
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 40
位數(shù)： 14
采樣率（每秒）： 540k
數(shù)據(jù)接口： 串行
設(shè)置時(shí)間： 20µs
DAC 型： 電壓
工作溫度： -40°C ~ 85°C
已供物品： 板，CD
已用 IC / 零件： AD5371
相關(guān)產(chǎn)品： AD5371BSTZ-REEL-ND - IC DAC 14BIT 40CH SER 80-LQFP
AD5371BBCZ-REELTR-ND - IC DAC 14BIT 40CH SER 100-CSPBGA
AD5371
Rev. B | Page 6 of 28
TIMING CHARACTERISTICS
DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = 16.5 V to 8 V; VREFx = 3 V; AGND = DGND = SIGGNDx = 0 V; CL = 200 pF to GND;
RL = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted.
Table 4. SPI Interface
Limit at TMIN, TMAX
Unit
Description
t1
20
ns min
SCLK cycle time
t2
8
ns min
SCLK high time
t3
8
ns min
SCLK low time
t4
11
ns min
SYNC falling edge to SCLK falling edge setup time
t5
20
ns min
Minimum SYNC high time
t6
10
ns min
24th SCLK falling edge to SYNC rising edge
t7
5
ns min
Data setup time
t8
5
ns min
Data hold time
42
ns max
SYNC rising edge to BUSY falling edge
t10
1/1.5
μs typ/μs max
BUSY pulse width low (single-channel update); see Table 9
t11
600
ns max
Single-channel update cycle time
t12
20
ns min
SYNC rising edge to LDAC falling edge
t13
10
ns min
LDAC pulse width low
t14
3
μs max
BUSY rising edge to DAC output response time
t15
0
ns min
BUSY rising edge to LDAC falling edge
t16
3
μs max
LDAC falling edge to DAC output response time
t17
20/30
μs typ/μs max
DAC output settling time
t18
140
ns max
CLR/RESET pulse activation time
t19
30
ns min
RESET pulse width low
t20
400
μs max
RESET time indicated by BUSY low
t21
270
ns min
Minimum SYNC high time in readback mode
25
ns max
SCLK rising edge to SDO valid
t23
80
ns max
RESET rising edge to BUSY falling edge
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
4 t9 is measured with the load circuit shown in Figure 2.
5 t22 is measured with the load circuit shown in Figure 3.
Table 5. LVDS Interface
Limit at TMIN, TMAX
Unit
Description
t1
12
ns min
SCLK cycle time
t2
5
ns min
SCLK pulse width high and low time
t3
5
ns min
SYNC to SCLK setup time
t4
3
ns min
Data setup time
t5
3
ns min
Data hold time
t6
3
ns min
SCLK to SYNC hold time
t7
10
ns min
SYNC high time
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-AD5372EBZ 功能描述:BOARD EVAL FOR AD5372 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
EVAL-AD5373EBZ 功能描述:BOARD EVAL FOR AD5373 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
EVAL-AD5379EB 制造商:AD 制造商全稱:Analog Devices 功能描述:40-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage-Output DAC
EVAL-AD5379EBZ 功能描述:BOARD EVALUATION FOR AD5379 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
EVAL-AD5380EB 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk
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