VDD = V
參數(shù)資料
型號(hào): EVAL-AD5258DBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 20/24頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD5258DBZ
標(biāo)準(zhǔn)包裝: 1
系列: *
Data Sheet
AD5258
Rev. D | Page 5 of 24
TIMING CHARACTERISTICS
VDD = VLOGIC = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; 40°C < TA < +85°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
I2C INTERFACE TIMING CHARACTERISTICS
SCL Clock Frequency
fSCL
0
400
kHz
tBUF Bus-Free Time Between Stop and Start
t1
1.3
s
tHD;STA Hold Time (Repeated start)
t2
After this period, the first clock pulse is
generated.
0.6
s
tLOW Low Period of SCL Clock
t3
1.3
s
tHIGH High Period of SCL Clock
t4
0.6
s
tSU;STA Setup Time for Repeated Start Condition
t5
0.6
s
tHD;DAT Data Hold Time
t6
0
0.9
s
tSU;DAT Data Setup Time
t7
100
ns
tF Fall Time of Both SDA and SCL Signals
t8
300
ns
tR Rise Time of Both SDA and SCL Signals
t9
300
ns
tSU;STO Setup Time for Stop Condition
t10
0.6
s
EEPROM Data Storing Time
tEEMEM_STORE
26
ms
EEPROM Data Restoring Time at Power On1
tEEMEM_RESTORE1
VDD rise time dependant. Measure with-
out decoupling capacitors at VDD and GND.
300
s
EEPROM Data Restoring Time upon Restore
Command1
tEEMEM_RESTORE2
VDD = 5 V.
300
s
EEPROM Data Rewritable Time2
tEEMEM_REWRITE
540
s
FLASH/EE MEMORY RELIABILITY
Endurance3
100
700
kCycles
Data Retention4
100
Years
1
During power-up, the output is momentarily preset to midscale before restoring EEPROM content.
2
Delay time after power-on preset prior to writing new EEPROM data.
3
Endurance is qualified to 100,000 cycles per JEDEC Std. 22 Method A117 and is measured at 40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
4
Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates
with junction temperature.
05029-
004
t1
SCL
SDA
P
S
P
t3
t2
t8
t9
t8
t9
t4
t5
t7
t6
t10
Figure 3. I2C Interface Timing Diagram
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