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| 型號： | EVAL-AD5064-1EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 27/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD5064-1 |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | nanoDAC™ |
| DAC 的數(shù)量： | 4 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 125k |
| 數(shù)據(jù)接口： | 串行 |
| 設(shè)置時間： | 8µs |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 125°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD5064 |
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AD5024/AD5044/AD5064
Data Sheet
Rev. F | Page 8 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
POR
VOUTC
VOUTA
VREFIN
DIN
GND
VOUTB
VOUTD
SDO
SCLK
CLR
VDD
LDAC
SYNC
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
AD5064-1
14
13
12
11
10
9
8
0
68
03
-0
65
Figure 6. 14-Lead TSSOP (RU-14)
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
LDAC
LDAC can be operated in two modes, asynchronously and synchronously, as shown in Figure 4. Pulsing
this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows
all DAC outputs to simultaneously update. This pin can also be tied permanently low in standalone mode.
When daisy-chain mode is enabled, this pin cannot be tied permanently low; the LDAC pin should be
used in asynchronous LDAC update mode, as shown in Figure 5, and the LDAC pin must be brought
high after pulsing.
2
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and DIN buffers and enables the shift register. Data is transferred in on the
falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge of
SYNC acts as an interrupt and the write sequence is ignored by the device.
3
VDD
Power Supply Input. These parts can be operated from 4.5 V to 5.5 V, and the supply should be decoupled
with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
4
VOUTA
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
5
VOUTC
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
6
POR
Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to VDD
powers up all four DACs to midscale.
7
VREFIN
This is a common pin for reference input for DAC A, DAC B, DAC C, and DAC D.
8
SDO
Serial Data Output. Can be used to daisy-chain a number of AD5064-1 devices together. The serial data
is transferred on the rising edge of SCLK and is valid on the falling edge of the clock.
9
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are
ignored. When CLR is activated, the input register and the DAC register are updated with the data
contained in the clear code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
10
VOUTD
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
11
VOUTB
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
12
GND
Ground Reference Point for All Circuitry on the Part.
13
DIN
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the shift register on the
falling edge of the serial clock input.
14
SCLK
Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data
can be transferred at rates of up to 50 MHz.
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