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參數(shù)資料
| 型號： | EVAL-AD2S1205SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/20頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD2S1205 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，旋轉(zhuǎn)變壓至數(shù)字 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD2S1205 |
| 主要屬性： | 12 位分辨率，最大 1250 rps 或 1024 脈沖/反向 |
| 已供物品： | 板 |
AD2S1205
Rev. A | Page 19 of 20
CONNECTING TO THE DSP
The AD2S1205 serial port is ideally suited for interfacing to DSP-
configured microprocessors. Figure 16 shows the AD2S1205
interfaced to an ADMC401, one of the DSP-based motor
controllers.
The on-chip serial port of the ADMC401 is used in the following
configuration
Alternate framing transmit mode with internal framing
(internally inverted)
Normal framing receive mode with external framing
(internally inverted)
Internal serial clock generation
In this configuration, the internal TFS signal of ADMC401
is used as an external RFS to fully control the timing of
data received, and the same TFS is connected to RD of the
AD2S1205. In addition, the ADMC401 provides an internal
continuous serial clock to the AD2S1205. The SAMPLE signal
on the AD2S1205 can be provided either by using a PIO or by
inverting the PWMSYNC signal to synchronize the position
and velocity readings with the PWM switching frequency. CS
and RDVEL can be obtained using two PIO outputs of the
ADMC401. The 12 bits of significant data and the status bits
are available on each consecutive negative edge of the clock
after the RD signal goes low. Data is clocked from the AD2S1205
into the data receive register of the ADMC401. This is internally
set to 16 bits (12 data bits, 4 status bits) because 16 bits are
received overall. The serial port automatically generates an
internal processor interrupt. This allows the ADMC401 to
read all 16 bits and then continue to process data.
All ADMC401 products can interface to the AD2S1205 by using
similar interface circuitry.
06
33
9-
0
16
SCLK
DR
TFS
RFS
PWMSYNC
PIO
SCLK
SOE
SO
RD
SAMPLE
CS
RDVEL
ADMC401
AD2S1205
Figure 16. Connecting to the ADMC401
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