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參數(shù)資料
| 型號(hào)： | EVAL-AD2S1200SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/24頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD2S1200 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，旋轉(zhuǎn)變壓至數(shù)字 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD2S1200 |
| 主要屬性： | 圖形用戶界面（GUI） |
| 已供物品： | 板，CD，電源 |
AD2S1200
Rev. 0 | Page 11 of 24
CONNECTING THE CONVERTER
Refer to Figure 5. Ground should be connected to the AGND
pin and DGND pin. Positive power supply VDD = +5 V dc ± 5%
should be connected to the AVDD pin and DVDD pin. Typical
values for the decoupling capacitors are 10 nF and 4.7 F,
respectively. These capacitors should be placed as close to the
device pins as possible, and should be connected to both AVDD
and DVDD. If desired, the reference oscillator frequency can be
changed from the nominal value of 10 kHz using FS1 and FS2.
Typical values for the oscillator decoupling capacitors are 20 pF.
Typical values for the reference decoupling capacitors are 10 F
and 0.01 F, respectively.
04406-0-005
DVDD
5V
1
2
3
4
5
6
7
8
9
10
11
RESET
33
32
31
30
29
28
27
26
25
24
DGND
8.912
MHz
20pF
4.7
F
10nF
23
12 13 14 15
DGND
16
DV
DD
17 18 19 20 21 22
44
RE
FBY
P
43
AGND
42
Cos
41
Cos
L
O
40
AV
DD
39
SinLO
38
Sin
37
AGND
36 35
EXC
34
AD2S1200
EXC
10
F
10nF
5V
S2
S6
S3
S1
4.7
F
10nF
5V
BUFFER
CIRCUIT
BUFFER
CIRCUIT
R2
R1
Figure 5. Connecting the AD2S1200 to a Resolver
The gain of the buffer depends on the type of resolver used.
Since the specified excitation output amplitudes are matched to
the specified Sin/Cos input amplitudes, the gain of the buffer is
determined by the attenuation of the resolver.
In this recommended configuration, the converter introduces a
VREF/2 offset in the Sin, Cos signals coming from the resolver.
Of course, the SinLO and CosLO signals may be connected to a
different potential relative to ground, as long as the Sin and Cos
signals respect the recommended specifications. Note that since
the EXC/EXC outputs are differential, there is an inherent gain
of 2×.
For example, if the primary to secondary turns ratio is 2:1, the
buffer will have unity gain. Likewise, if the turns ratio is 5:1, the
gain of the buffer should be 2.5×. Figure 6 suggests a buffer
circuit. The gain of the circuit is
)
1
/
2
(
R
Gain
=
and
×
+
×
=
IN
REF
OUT
V
R
V
1
2
1
2
1
VREF is set so that VOUT is always a positive value, eliminating the
need for a negative supply.
04406-0-006
12V
EXC/EXC
(VIN)
5V
(VREF)
R2
12V
VOUT
33
33
R1
442
1.24k
12V
2.7k
2.7k
Figure 6. Buffer Circuit
Separate screened twisted cable pairs are recommended for
analog inputs Sin/SinLO and Cos/CosLO. The screens should
terminate to REFOUT. To achieve the dynamic performance
specified, an 8.192 MHz crystal must be used.
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