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參數(shù)資料
| 型號(hào)： | EVAL-AD1833EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multichannel 24-Bit, 192 kHz, DAC |
| 中文描述： | 多通道24位，192千赫，數(shù)模轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 3/20頁(yè) |
| 文件大?。?/td> | 687K |
| 代理商： | EVAL-AD1833EB |
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REV. 0
–3–
AD1833A
Parameter
Min
Typ
Max
Unit
Test Conditions
DIGITAL I/O
Input Voltage HI
Input Voltage LO
Output Voltage HI
Output Voltage LO
2.4
V
V
V
V
0.8
DV
DD2
– 0.4
0.4
POWER SUPPLIES
Supply Voltage (AV
DD
and DV
DD1
)
Supply Voltage (DV
DD2
)
Supply Current I
ANALOG
Supply Current I
DIGITAL
4.5
3.3
5
5.5
DV
DD1
42
48
V
V
mA
mA
mA
38.5
42
2
Active
Power-Down
Power Supply Rejection Ratio
1 kHz 300 mV p-p Signal at Analog Supply Pins
20 kHz 300 mV p-p Signal at Analog Supply Pins
–60
–50
dB
dB
Specifications subject to change without notice.
DIGITAL TIMING
Parameter
Min
Max
Unit
Comments
MASTER CLOCK AND RESET
t
ML
MCLK LO (All Modes)
*
t
MH
MCLK HI (All Modes)
*
t
PDR
PD
/
RST
LO
SPI PORT
t
CCH
CCLK HI Pulsewidth
t
CCL
CCLK LO Pulsewidth
t
CCP
CCLK Period
t
CDS
CDATA Setup Time
t
CDH
CDATA Hold Time
t
CLS
CLATCH Setup
t
CLH
CLATCH Hold
DAC SERIAL PORT
t
DBH
BCLK HI
t
DBL
BCLK LO
t
DLS
L/RCLK Setup
t
DLH
L/RCLK Hold
t
DDS
SDATA Setup
t
DDH
SDATA Hold
TDM MODE MASTER
t
TMBD
BCLKTDM Delay
t
TMFSD
FSTDM Delay
t
TMDDS
SDIN1 Setup
t
TMDDH
SDIN1 Hold
TDM MODE SLAVE
f
TSB
BCLKTDM Frequency
t
TSBCH
BCLKTDM High
t
TSBCL
BCLKTDM Low
t
TSFS
FSTDM Setup
t
TSFH
FSTDM Hold
t
TSDDS
SDIN1 Setup
t
TSDDH
SDIN1 Hold
AUXILIARY INTERFACE
t
AXLRD
L/RCLK Delay
t
AXDD
Data Delay
t
AXBD
AUXBCLK Delay
15
15
20
ns
ns
ns
24 MHz clock, clock doubler bypassed
24 MHz clock, clock doubler bypassed
20
20
80
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
To CCLK rising
From CCLK rising
To CCLK rising
From CCLK rising
15
15
10
10
10
15
ns
ns
ns
ns
ns
ns
To BCLK rising
From BCLK rising
To BCLK rising
From BCLK rising
20
10
ns
ns
ns
ns
From MCLK rising
From BCLKTDM rising
To BCLKTDM falling
From BCLKTDM falling
15
15
256 f
S
20
20
10
10
15
15
ns
ns
ns
ns
ns
ns
To BCLKTDM falling
From BCLKTDM falling
To BCLKTDM falling
From BCLKTDM falling
10
10
20
ns
ns
ns
From BCLK falling
From BCLK falling
From MCLK rising
*
MCLK symmetry must be better than 60:40 or 40:60.
Specifications subject to change without notice.
(Guaranteed over –40 C to +85 C, AV
DD
= DV
DD
= 5 V
10%)
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