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參數(shù)資料
| 型號(hào)： | EVAL-AD1833AEB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 24-Bit, 192 kHz, DAC |
| 中文描述： | 24位，192千赫，數(shù)模轉(zhuǎn)換器 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大小： | 687K |
| 代理商： | EVAL-AD1833AEB |
REV. 0
AD1833A
–16–
Packed Mode 128
In Packed Mode 128, all six data channels are packed into one
sample interval on one data pin. The BCLK runs at 128 f
S
;
therefore, there are 128 BCLK periods in each sample interval.
Each sample interval is broken into eight time slots: six slots of
20 BCLK and two of 4 BCLK. In this mode, the data length is
restricted to a maximum of 20 bits. The three left channels are
written first, MSB first, and the data is written on the falling
edge of BCLK. After the three left channels are written, there is
a space of four BCLK, and then the three right channels are writ-
ten. The L/
R
CLK defines the left and right data transmission; it
is high for the three left channels and low for the three right channels.
Packed Mode 256
In Packed Mode 256, all six data channels are packed into one
sample interval on one data pin. The BCLK runs at 256 f
S
;
therefore, there are 256 BCLK periods in each sample interval, and
each sample interval is broken into eight time slots of 32 BCLK
each. The data length can be 16, 20, or 24 bits. The three left
channels are written first, MSB first, and the data is written on the
falling edge of BCLK with a one BCLK period delay from the
start of the slot. After the three left channels are written, there is
a space of 32 BCLK, and then the three right channels are written.
The
L
/RCLK defines the left and right data transmission; it is
low for the three left channels and high for the three right channels.
SLOT 1
LEFT 0
SLOT 2
LEFT 1
SLOT 3
LEFT 2
BLANK SLOT
4 SCLK
SLOT 4
RIGHT 0
SLOT 5
RIGHT 1
SLOT 6
RIGHT 2
BLANK SLOT
4 SCLK
DATA
20-BIT DATA
16-BIT DATA
BCLK
BCLK
–1
–2
–3
–4
–1
–2
–3
–4
+4
+3
+2
+1
MSB
LSB
LSB
MSB
L/
R
CLK
Figure 11. Packed Mode 128
SLOT 1
LEFT 0
SLOT 2
LEFT 1
SLOT 3
LEFT 2
SLOT 4
RIGHT 0
SLOT 5
RIGHT 1
SLOT 6
RIGHT 2
20-BIT DATA
24-BIT DATA
16-BIT DATA
BCLK
–1
–2
–3
–4
–1
–2
–3
–4
+8
+7
+6
+5
+4
+3
+2
+1
+4
+3
+2
+1
MSB
LSB
LSB
LSB
MSB
–1
–2
–3
–4
MSB
DATA
BCLK
L
/RCLK
Figure 12. Packed Mode 256
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PDF描述 |
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| EVAL-AD1833EB | Multichannel 24-Bit, 192 kHz, DAC |
| EVAL-AD1837EB | 2 ADC, 8 DAC, 96 kHz, 24-Bit Codec |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD1833EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multichannel 24-Bit, 192 kHz, DAC |
| EVAL-AD1835AEB | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
| EVAL-AD1835EB | 制造商:Analog Devices 功能描述:Evaluation Board For AD1835 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
| EVAL-AD1836AEB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multichannel 96 kHz Codec |
| EVAL-AD1837AEB | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
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