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參數(shù)資料
| 型號： | ET80960JT10016 |
| 廠商： | Intel |
| 文件頁數(shù)： | 13/86頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU I960JT 3V 100MHZ 132-QFP |
| 標準包裝： | 1 |
| 處理器類型： | i960 |
| 特點： | 后綴 JT，32 位 16K 高速緩沖 |
| 速度： | 100MHz |
| 電壓： | 3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 132-QFP |
| 供應商設備封裝： | 132-QFP |
| 包裝： | 托盤 |
| 其它名稱： | 864017 |
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80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
20
Datasheet
DEN#
O
R(1)
H(Z)
P(1)
DATA ENABLE indicates data transfer cycles during a bus access. DEN# is
asserted at the start of the first data cycle in a bus access and deasserted at the end
of the last data cycle. DEN# is used with DT/R# to provide control for data
transceivers connected to the data bus.
0 = data cycle
1 = not data cycle
BLAST#
O
R(1)
H(Z)
P(1)
BURST LAST indicates the last transfer in a bus access. BLAST# is asserted in the
last data transfer of burst and non-burst accesses. BLAST# remains active as long
as wait states are inserted through the RDYRCV# pin. BLAST# becomes inactive
after the final data transfer in a bus cycle.
0 = last data transfer
1 = not last data transfer
RDYRCV#
I
S(L)
READY/RECOVER indicates that data on AD lines may be sampled or removed.
When RDYRCV# is not asserted during a Td cycle, the Td cycle is extended to the
next cycle by inserting a wait state (Tw).
0 = sample data
1 = don’t sample data
The RDYRCV# pin has another function during the recovery (Tr) state. The
processor continues to insert additional recovery states until it samples the pin
HIGH. This function gives slow external devices more time to float their buffers
before the processor begins to drive address again.
0 = insert wait states
1 = recovery complete
LOCK#/
ONCE#
I/O
S(L)
R(H)
H(Z)
P(1)
BUS LOCK indicates that an atomic read-modify-write operation is in progress. The
LOCK# output is asserted in the first clock of an atomic operation and deasserted in
the last data transfer of the sequence. The processor does not grant HOLDA while it
is asserting LOCK#. This prevents external agents from accessing memory involved
in semaphore operations.
0 = Atomic read-modify-write in progress
1 = Atomic read-modify-write not in progress
ONCE MODE: The processor samples the ONCE# input during reset. When it is
asserted LOW at the end of reset, the processor enters ONCE mode. In ONCE
mode, the processor stops all clocks and floats all output pins. The pin has a weak
internal pullup which is active during reset to ensure normal operation when the pin
is left unconnected.
0 = ONCE mode enabled
1 = ONCE mode not enabled
HOLD
I
S(L)
HOLD: A request from an external bus master to acquire the bus. When the
processor receives HOLD and grants bus control to another master, it asserts
HOLDA, floats the address/data and control lines and enters the Th state. When
HOLD is deasserted, the processor deasserts HOLDA and enters either the Ti or Ta
state, resuming control of the address/data and control lines.
0 = no hold request
1 = hold request
Table 8.
Pin Description—External Bus Signals (Sheet 3 of 4)
NAME
TYPE
DESCRIPTION
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| ET80960KA20512 | 功能描述:IC MPU I960KA 20MHZ 132-QFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應商設備封裝:357-PBGA（25x25） 包裝:托盤 |
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