6
SAM0378-053001
ESS Technology, Inc.
ES4228/ES4227 PRODUCT BRIEF
ES4227 PIN DESCRIPTION
Table 2 lists the pin descriptions for the ES4227.
Table 2 ES4227 Pin Descriptions List
Name
Number
1, 25:26, 31, 72,
75, 77, 91, 100
5, 16, 32, 66,
73, 78, 90
DSC_C
AUX0
AUX1
AUX2
AUX3
AUX4
AUX5
AUX6
AUX7
AUX8
AUX9
AUX10
AUX11
AUX12
AUX13
AUX14
AUX15
8, 81, 83, 85,
93, 95, 97, 99
DSC_S
DCLK
EXT_CLK
RESET#
MUTE
MCLK
TWS
SPLL_OUT
TSD
TBCK
RWS
I/O
I
Definition
VSS
Ground.
VCC
I
5.0V power supply.
6
7
9
11
70
69
68
67
14
18
20
34
35
36
38
39
40
I
Clock for programming to access internal registers.
General purpose I/O.
General purpose I/O.
General purpose I/O.
CD loader reset.
Modem DSP reset.
General purpose I/O.
General purpose I/O.
General purpose I/O.
General purpose I/O.
General purpose I/O.
General purpose I/O.
Interrupt output to ES4228.
CD loader C2PO.
General purpose I/O.
Interrupt input from Modem DSP.
IR interrupt Input.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DSC_D[7:0]
Data for programming to access internal registers.
10
12
I
Strobe for programming to access internal registers.
Dual-purpose pin DCLK is the ES4228 clock.
External clock input during bypass PLL mode.
Reset.
Audio mute.
Audio master clock.
Dual-purpose pin TWS is the transmit audio frame sync.
SPLL_OUT is the select PLL output.
Transmit audio data input.
Transmit audio bit clock.
Dual-purpose pin RWS is the receive audio frame sync.
Pins SEL_PLL[1:0] select the PLL clock frequency for the DCLK output.
O
I
I
O
I
I
O
I
I
O
I
13
15
17
19
21
22
23
SEL_PLL1
RSTOUT#
NC
24
O
Reset output (active-low).
No connect. Do not connect to these pins.
2:4,27:30,76
SEL_PLL1
0
0
1
1
SEL_PLL0
0
1
0
1
DCLK
Bypass PLL (input mode)
27 MHz (output mode) Default
32.4 MHz (output mode)
40.5 MHz (output mode)