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參數(shù)資料
| 型號： | ES4118F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Super VCD Processor Product Brief |
| 中文描述： | 超級VCD處理器產(chǎn)品簡介 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 65K |
| 代理商： | ES4118F |
3
SAM0422-052901
ESS Technology, Inc.
ES4118 PRODUCT BRIEF
ES4118 PIN DESCRIPTION
Table 1 lists the ES4118 pin descriptions.
Table 1 ES4118 Pin Descriptions List
Name
Number
I/O
Definition
VCC
1, 9, 18, 27, 35, 44,
51, 59, 68, 75, 83, 92,
99, 104, 111, 121, 130,
139, 148, 157, 164,
172, 183, 193, 201
I
3.3V power supply.
LA[21:0]
7:2, 16:10, 23:19,
207:204
O
Device address output.
VSS
8, 17, 26, 34, 43, 52,
60, 67, 76, 84, 91, 98,
103, 112, 120, 129,
138, 147, 156, 163,
171, 177, 184, 192,
200, 208
I
Ground.
RESET#
24
I
Reset input, active low.
TDMDX
25
O
TDM transmit data.
RSEL
I
ROM Select.
RSEL
TDMDR
28
I
TDM receive data.
TDMCLK
29
I
TDM clock input.
TDMFS
30
I
TDM frame sync.
TDMTSC#
31
O
TDM output enable.
TWS
32
O
Audio transmit frame sync.
TSD
33
O
Audio transmit serial data port.
SEL_PLL0
I
Select PLL0:
SEL_PLL2
0
0
1
1
SEL_PLL2
36
I
Select PLL2. (Refer to the definitions table in pin number 33.)
NC
37, 38, 41, 42,
142:146, 149:155,
158, 202, 203
No connect.
MCLK
39
I/O
Audio master clock for audio DAC.
TBCK
40
I/O
Audio transmit bit clock.
RSD
45
I
Audio receive serial data.
RWS
46
I
Audio receive frame sync.
RBCK
47
I
Audio receive bit clock.
APLLCAP
48
I
Analog PLL capacitor.
XIN
49
I
Crystal input.
XOUT
50
O
Crystal output.
DMA[11:0]
53:58, 61:66
O
DRAM address bus.
DCAS#
69
O
DRAM column address strobe.
DOE#
70
O
DRAM output enable.
DSCK_EN
O
DRAM clock enable
DWE#
71
O
DRAM write enable.
DRAS[2:0]#
74:72
O
DRAM row address strobe.
DB[15:0]
77:82, 85:90, 93:96
I/O
DRAM data bus.
DCS[1:0]#
97, 100
O
SDRAM chip select [1:0], active low.
DQM
101
O
Data input/output mask.
DSCK
102
O
Clock to SDRAM.
Selection
16-bit ROM
8-bit ROM.
0
1
SEL_PLL1 SEL_PLL0 Notes
0
1
0
1
2.5 x DCLK
3 x DCLK
3.5 x DCLK
4 x DCLK.
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