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參數資料
| 型號： | ES29DL800FT-90RTGI |
| 廠商： | 優(yōu)先(蘇州)半導體有限公司 |
| 英文描述： | 4Mbit(512Kx 8/256K x 16) CMOS 3.0 Volt-only, Boot Sector Flash Memory |
| 中文描述： | 的4Mb（512Kx 8/256K × 16），3.0伏的CMOS只，引導扇區(qū)閃存 |
| 文件頁數： | 18/51頁 |
| 文件大?。?/td> | 697K |
| 代理商： | ES29DL800FT-90RTGI |
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ESI
18
Rev.0B January 5, 2006
ES29LV400E
Excel Semiconductor inc.
reset immediately terminates the erase operation.If
that occurs, the chip erase command sequence
should be reinitiated once the device has returned to
reading array data. to ensure data integrity. Fig. 7
illustrates the algorithm for the erase operation.
Refer to the Erase and Program Operations tables in
the AC Characteristics section for parameters, and
Fig. 21 section for timing diagrams.
SECTOR ERASE COMMAND
By using a sector erase command, a single sector or
multiple sectors can be erased. The sector erase
command is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Table 5 shows the
address and data requirements for the sector erase
command sequence. Note that the autoselect is
unavailable while an erase operation is in progress.
Embedded Sector Erase Algorithm
The device does not require the system to prepro-
gram prior to erase. The Embedded Erase algorithm
automatically programs and verifies the entire mem-
ory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings these operations.
Sector Erase Time-out Window and DQ3
After the command sequence is written, a sector
erase time-out of
50us
occurs. During the time-out
period, additional sector addresses and sector erase
commands may be written. Loading the sector erase
buffer may be done in any sequence, and the num-
ber of sectors may be from one sector to all sectors.
The time between these additional cycles must be
less than 50 us, otherwise the last address and com-
mand may not be accepted, and erasure may begin.
It is recommended that processor interrupts be dis-
abled during this time to ensure all commands are
accepted. The interrupts can be re-enabled after the
last Sector Erase command is written. The system
can monitor
DQ3
to determine if the sector erase
timer has timed out (See the section on DQ3:Sector
Erase Timer.). The time-out begins from the rising
edge of the final WE# pulse in the command
sequence.
Any command other than Sector Erase or Erase Sus-
pend during the time-out period resets the device
to the read mode. The system must rewrite the
command sequence and any additional addresses
and commands.
Status Bits : DQ7,DQ6,DQ2, or RY/BY#
When the Sector Erase Embedded Erase algorithm
is complete, the device returns to reading array
data and addresses are no longer latched. Note
that while the Embedded Erase operation is in
progress, the system can read data from the non-
erasing sector. The system can determine the sta-
tus
of
the
erase
DQ7,DQ6,DQ2, or RY/BY# in the erasing sector.
Refer to the Write Operation Status section Table 6
for information on these status bits.
operation
by
reading
Valid Command during Sector Erase
Once the sector erase operation has begun, only
the Erase Suspend command is valid. All other
commands are ignored. However, note that a
hard-
ware reset
immediately terminates the erase oper-
ation. If that occurs, the sector erase command
START
No
No
Yes
Write Erase
Command Sequence
(Notes 1,2)
Data Poll to
Erasing Bank
from System
Data = FFh
Erasure Completed
Embedded
Erase
algorithm in
progress
Notes:
1. See Table 5 for erase command sequence
2. See the section on DQ3 for information on the sector erase timer
Figure 7. Erase Operation
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