參數(shù)資料
型號: ES29BDS320FB-12RTG
廠商: 優(yōu)先(蘇州)半導體有限公司
英文描述: 8Mbit(1M x 8/512K x 16) CMOS 3.0 Volt-only, Boot Sector Flash Memory
中文描述: 8Mbit(3米x 8/512K × 16),3.0伏的CMOS只,引導扇區(qū)閃存
文件頁數(shù): 45/50頁
文件大小: 696K
代理商: ES29BDS320FB-12RTG
ESI
45
Rev. 0A January 5, 2006
ES29LV800E
Excel Semiconductor inc.
PARALLEL TO
SEATING PLANE
θ°
L
R
c
0.25MM
(0.0098”) BSC
B
B
A
SEE DETAIL A
DETAIL A
-A-
-B-
SEE DETAIL B
D1
D
N
2
----
N
2
----
1
+
A2
0.10 C
e
A1
-C-
SEATING
PLANE
GAUGE
PLANE
-X-
e/2
X = A OR B
b
c1
b1
(c)
WITH
PLATING
BASE
METAL
DETAIL B
SECTION B-B
0.08MM (0.0031”)
M
C A-B S
2
1
N
E
5
4
5
9
6 7
7
Package
TS 48
JEDEC
MO-142 (B) DD
Symbol
MIN
NOM
MAX
A
-
-
1.20
A1
0.05
-
0.15
A2
0.95
1.00
1.05
b1
0.17
0.20
0.23
b
0.17
0.22
0.27
c1
0.10
-
0.16
c
0.10
-
0.21
D
19.80
20.00
20.20
D1
18.30
18.40
18.50
E
11.90
12.00
12.10
e
0.50 BASIC
L
θ
0.50
0.60
0.70
R
0.08
-
0.20
N
48
0
°
5
°
3
°
NOTES:
1. Controlling dimensions are in millimeters(mm). (Dimensioning
and tolerancing conforms to ANSI Y14.5M-1982)
2.
Pin 1
identifier for standard pin out (Die up).
3.
Pin 1
identifier for reverse pin out (Die down): Ink or Laser mark
4. To be determined at the seating plane. The seating plane is def-
ined as the plane of contact that is made when the package lea-
ds are allowed to rest freely on a flat horizontal surface.
5. Dimension
D1
and
E
do not include mold protrusion. Allowable
mold protrusion is 0.15mm (0.0059”) per side.
6. Dimension
b
does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.0031”) total in excess
of
b
dimension at max. material condition. Minimum space
between protrusion and an adjacent lead to be 0.07mm
(0.0028”).
7. These dimensions apply to the flat section of the lead between
0.10mm (0.0039”) and 0.25mm (0.0098”) from the lead tip.
8. Lead coplanarity shall be within 0.10mm (0.004”) as measured
from the seating plane.
9. Dimension “
e
” is measured at the centerline of the leads.
PHYSICAL DIMENSIONS
48-Pin Standard TSOP (measured in millimeters)
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