參數(shù)資料
型號： ES25P80-75IC2T
廠商： 優(yōu)先(蘇州)半導(dǎo)體有限公司
英文描述： 8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface
中文描述： 8Mbit的CMOS 3.0伏的閃存與75MHz的SPI總線接口
文件頁數(shù)： 12/35頁
文件大?。?/td> 450K
代理商： ES25P80-75IC2T
ESI
12
Rev. 0D May, 11, 2006
ES25P80
Excel Semiconductor inc.
ADVANCED INFORMATION
0 0 0 0 0 1 0 1
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows
the Status Register to be read. The Status Register
may be read at any time, even while a Program,
Erase, or Write Status Register cycle is in progress.
When one of these cycles is in progress, it is recom-
mended to check the Write In Progress (WIP) bit
before sending a new instruction to the device. It is
also possible to read the Status Register continu-
ously, as shown in Figure 6.
The status and control bits of the Status Register are
as follows :
WIP bit
The Write In Progress (WIP) bit indicates whether
the memory is busy with a Write Status Register,
Program or Erase cycle. This bit is a read only bit
and is read by executing a RDSR instruction. If this
bit is 1, such a cycle is in progress, if it is 0, no such
cycle is in progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the sta-
tus of the internal Write Enable Latch. When set to 1,
the internal Write Enable Latch is set; when set to 0,
the internal Write Enable Latch is reset and no Write
Status Register, Program or Erase instruction is
accepted.
BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-vol-
atile. They define the size of the area to be software
protected against Program and Erase instructions.
These bits are written with the Write Status Register
(WRSR) instruction. When one or both of the Block
Protect (BP2, BP1, BP0) bits is set to 1, the relevant
memory area (as defined in Table 1) becomes pro-
tected against Page Program (PP), and Sector
Erase (SE) instructions. The Block Protect (BP2,
BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set. The
Bulk Erase (BE) instruction is executed if, and only
if, all Block Protect (BP2, BP1, BP0) bits are 0.
SRWD bit
The Status Register Write Disable (SRWD) bit is
operated in conjunction with the Write Protect (W#)
signal. The Status Register Write Disable (SRWD)
bit and Write Protect (W#) signal allow the device to
be put in the Hardware Protected mode (when the
Status Register Write Disable (SRWD) bit is set to 1,
and Write Protect (W#) is driven Low). In this mode,
the non-volatile bits of the Status Register (SRWD,
BP2, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no
longer accepted for execution.
Figure 6. Read Status Register (RDSR) Instruction Sequence
SCK
CS#
SI
SO
Status Register Out
Status Register Out
MSB
MSB
7
Instruction
High Impedance
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
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