參數(shù)資料
型號(hào)： ES25P40
廠商： 優(yōu)先(蘇州)半導(dǎo)體有限公司
英文描述： 4Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface
中文描述： 3.0伏特的4Mb的CMOS閃存的75MHz的SPI總線接口
文件頁(yè)數(shù)： 21/35頁(yè)
文件大?。?/td> 449K
代理商： ES25P40
ESI
21
Rev. 0D May 11 , 2006
ES25P40
Excel Semiconductor inc.
ADVANCED INFORMATION
1
0 1 1 1 0 0 1
Deep Power Down (DP)
The Deep Power Down (DP) instruction puts the
device in the lowest current mode of 1uA typical.
It is recommended that the standard Standby mode
be used for the lowest power current draw, as well as
the Deep Power Down (DP) as an extra software
protection mechanism when this device is not in
active use. In this mode, the device ignores all Write,
Program and Erase instructions. Chip Select (CS#)
must be driven Low for the entire duration of the
sequence.
The Deep Power Down (DP) instruction is entered by
driving Chip Select (CS#) Low, followed by the
instruction code on Serial Data Input (SI). Chip
Select (CS#) must be driven Low for the entire dura-
tion of the sequence.
The instruction sequence is shown in Figure 16.
Driving Chip Select (CS#) High after the eighth bit of
the instruction code has been latched puts the device
in Deep Power Down mode.
The Deep Power Down mode can only be entered
by executing the Deep Power Down (DP) instruc-
tion to reduce the standby current (from I
SB
to I
DP
as specified in Table 6). As soon as Chip Select
(CS#) is driven high, it requires a delay of t
DP
cur-
rently in progress before Deep Power Down mode
is entered.
Once the device has entered the Deep Power
Down mode, all instructions are ignored except the
Release from Deep Power Down (RES) and Read
Electronic Signature. This releases the device from
the Deep Power Down mode. The Release from
Deep Power Down and Read Electronic Signature
(RES) instruction also allows the Electronic Signa-
ture of the device to be output on Serial Data Out-
put (SO).
The Deep Power Down mode automatically stops
at Power-down, and the device always powers up
in the Standby mode.
Any Deep Power Down (DP) instruction, while an
Erase, Program or WRSR cycle is in progress, is
rejected without having any effect on the cycle in
progress.
Figure 16. Deep Power Down ( DP ) Instruction Sequence
CS#
SI
Standby Mode
Instruction
Deep Power
Down Mode
t
DP
0
1 2 3 4 5 6 7
SCK
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ES25P80-75CC2R 制造商:EXCELSEMI 制造商全稱:EXCELSEMI 功能描述:8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface
ES25P80-75CC2T 制造商:EXCELSEMI 制造商全稱:EXCELSEMI 功能描述:8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface
ES25P80-75CC2Y 制造商:EXCELSEMI 制造商全稱:EXCELSEMI 功能描述:8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface
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