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參數(shù)資料
| 型號(hào)： | EPM9560A |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Logic Device Family(MAX9000可編程邏輯系列器件) |
| 中文描述： | 可編程邏輯器件系列（MAX9000可編程邏輯系列器件） |
| 文件頁數(shù)： | 23/41頁 |
| 文件大?。?/td> | 604K |
| 代理商： | EPM9560A |
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Altera Corporation
23
MAX 9000 Programmable Logic Device Family Data Sheet
Programmable
Speed/Power
Control
MAX 9000 devices offer a power-saving mode that supports low-power
operation across user-defined signal paths or the entire device. Because
most logic applications require only a small fraction of all gates to operate
at maximum frequency, this feature allows total power dissipation to be
reduced by 50
%
or more.
The designer can program each individual macrocell in a MAX 9000
device for either high-speed (i.e., with the Turbo Bit
option turned on) or
low-power (i.e., with the Turbo Bit option turned off) operation. As a
result, speed-critical paths in the design can run at high speed, while
remaining paths operate at reduced power. Macrocells that run at low
power incur a nominal timing delay adder (
t
LPA
) for the LAB local array
delay (
t
LOCAL
).
Design Security
All MAX 9000 EPLDs contain a programmable security bit that controls
access to the data programmed into the device. When this bit is
programmed, a proprietary design implemented in the device cannot be
copied or retrieved. This feature provides a high level of design security,
because programmed data within EEPROM cells is invisible. The security
bit that controls this function, as well as all other programmed data, is
reset only when the device is erased.
Generic Testing
MAX 9000 EPLDs are fully functionally tested. Complete testing of each
programmable EEPROM bit and all logic functionality ensures 100
%
programming yield. AC test measurements are taken under conditions
equivalent to those shown in
Figure 12
. Test patterns can be used and then
erased during the early stages of the production flow.
Figure 12. MAX 9000 AC Test Conditions
VCC
To Test
System
C1 (includes
JIG capacitance)
Device input
rise and fall
times < 3 ns
Device
Output
464
(703
)
250
(8.06 K
)
Power supply transients can affect AC
measurements. Simultaneous transitions of
multiple outputs should be avoided for
accurate measurement. Threshold tests
must not be performed under AC
conditions. Large-amplitude, fast ground-
current transients normally occur as the
device outputs discharge the load
capacitances. When these transients flow
through the parasitic inductance between
the device ground pin and the test system
ground, significant reductions in
observable noise immunity can result.
Numbers in parentheses are for 3.3-V
outputs. Numbers without parentheses are
for 5.0-V devices or outputs.
相關(guān)PDF資料 |
PDF描述 |
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| EPS12 | TRANSIENT VOLTAGE SUPPESSOR |
| EPS15 | TRANSIENT VOLTAGE SUPPESSOR |
| EPS17 | TRANSIENT VOLTAGE SUPPESSOR |
| EPS24 | TRANSIENT VOLTAGE SUPPESSOR |
| EPS28 | TRANSIENT VOLTAGE SUPPESSOR |
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| EPM9560ABC356-10 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 9000 560 Macro 216 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM9560ABI356-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| EPM9560ARC208-10 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 9000 560 Macro 153 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM9560ARC208-10N | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 9000 560 Macro 153 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM9560ARC240-10 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 9000 560 Macro 191 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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