參數(shù)資料
型號： EPM7512B
廠商： Altera Corporation
英文描述： Programmable Logic Device Family(MAX7000B可編程邏輯系列器件)
中文描述： 可編程邏輯器件系列（MAX7000B可編程邏輯系列器件）
文件頁數(shù)： 4/125頁
文件大?。?/td> 1053K
代理商： EPM7512B
4
Altera Corporation
MAX 7000B Programmable Logic Device Family Data Sheet
Preliminary Information
The MAX 7000B architecture supports 100
%
TTL emulation and high-
density integration of SSI, MSI, and LSI logic functions. It easily integrates
multiple devices ranging from PALs, GALs, and 22V10s to MACH and
pLSI devices. MAX 7000B devices are available in a wide range of
packages, including PLCC, BGA, FineLine BGA, 0.8-mm Ultra FineLine
BGA, PQFP, TQFP, and VTQFP packages. See
Table 3
.
Notes:
(1)
(2)
Contact Altera for up-to-date information on available device package options.
When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programming or boundary-scan testing, four I/ O
pins become JTAG pins.
All 0.8-mm BGA packages are footprint-compatible via the SameFrame
TM
pin-out feature. Therefore, designers can
design a board to support a variety of devices, providing a flexible migration path across densities and pin counts.
Device migration is fully supported by Altera development tools. See
“SameFrame Pin-Outs” on page 14
for more
details.
All FineLine BGA packages are footprint-compatible via the SameFrame pin-out feature. Therefore, designers can
design a board to support a variety of devices, providing a flexible migration path across densities and pin counts.
Device migration is fully supported by Altera development tools. See
“SameFrame Pin-Outs” on page 14
for more
details.
(3)
(4)
MAX 7000B devices use CMOS EEPROM cells to implement logic
functions. The user-configurable MAX 7000B architecture accommodates
a variety of independent combinatorial and sequential logic functions.
The devices can be reprogrammed for quick and efficient iterations
during design development and debug cycles, and can be programmed
and erased up to 100 times.
MAX 7000B devices contain 32 to 512 macrocells that are combined into
groups of 16 macrocells, called logic array blocks (LABs). Each macrocell
has a programmable-
AND
/ fixed-
OR
array and a configurable register with
independently programmable clock, clock enable, clear, and preset
functions. To build complex logic functions, each macrocell can be
supplemented with both shareable expander product terms and high-
speed parallel expander product terms to provide up to 32 product terms
per macrocell.
Table 3. MAX 7000B Maximum User I/O Pins
Notes (1)
,
(2)
Device
44-Pin
PLCC
44-Pin
TQFP
48-Pin
VTQFP
49-Pin
0.8-mm
Ultra
FineLine
BGA
(3)
100-
Pin
TQFP
100-Pin
FineLine
BGA
(4)
144-
Pin
TQFP
169-Pin
0.8-mm
Ultra
FineLine
BGA
(3)
208-
Pin
PQFP
256-
Pin
BGA
256-Pin
FineLine
BGA
(4)
EPM7032B
36
36
36
EPM7064B
36
36
36
V
V
(1)
68
68
V
V
V
(1)
68
EPM7128B
40
(1)
84
84
100
(1)
100
EPM7256B
84
84
120
(1)
164
164
EPM7512B
84
120
176
212
212
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPM7512BBC256-10 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 512 Macro 212 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7512BBC256-5 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 512 Macro 212 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7512BBC256-7 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 512 Macro 212 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7512BBI256-7 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Altera Corporation 功能描述:
EPM7512BFC256-10 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 512 Macro 212 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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